Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 18 | #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | |
| 20 | /* Chipset types */ |
| 21 | #define SANDYBRIDGE_MOBILE 0 |
| 22 | #define SANDYBRIDGE_DESKTOP 1 |
| 23 | #define SANDYBRIDGE_SERVER 2 |
| 24 | |
| 25 | /* Device ID for SandyBridge and IvyBridge */ |
| 26 | #define BASE_REV_SNB 0x00 |
| 27 | #define BASE_REV_IVB 0x50 |
| 28 | #define BASE_REV_MASK 0x50 |
| 29 | |
| 30 | /* SandyBridge CPU stepping */ |
| 31 | #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ |
| 32 | #define SNB_STEP_D1 (BASE_REV_SNB + 6) |
| 33 | #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ |
| 34 | |
| 35 | /* IvyBridge CPU stepping */ |
| 36 | #define IVB_STEP_A0 (BASE_REV_IVB + 0) |
| 37 | #define IVB_STEP_B0 (BASE_REV_IVB + 2) |
| 38 | #define IVB_STEP_C0 (BASE_REV_IVB + 4) |
| 39 | #define IVB_STEP_K0 (BASE_REV_IVB + 5) |
| 40 | #define IVB_STEP_D0 (BASE_REV_IVB + 6) |
| 41 | |
| 42 | /* Intel Enhanced Debug region must be 4MB */ |
Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 43 | |
| 44 | #define IED_SIZE CONFIG_IED_REGION_SIZE |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | |
| 46 | /* Northbridge BARs */ |
| 47 | #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 48 | #ifndef __ACPI__ |
| 49 | #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ |
| 50 | #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ |
| 51 | #else |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 52 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 53 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 54 | #endif |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 55 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 56 | #define DEFAULT_RCBABASE ((u8 *)0xfed1c000) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 57 | |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 58 | #define IOMMU_BASE1 0xfed90000ULL |
| 59 | #define IOMMU_BASE2 0xfed91000ULL |
| 60 | |
Stefan Reinauer | e5a0a5d | 2012-09-19 10:51:48 -0700 | [diff] [blame] | 61 | #include <southbridge/intel/bd82x6x/pch.h> |
Arthur Heymans | d2d2aef | 2018-01-16 14:19:37 +0100 | [diff] [blame] | 62 | #include <southbridge/intel/common/rcba.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 63 | |
| 64 | /* Everything below this line is ignored in the DSDT */ |
| 65 | #ifndef __ACPI__ |
| 66 | |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 67 | #include <rules.h> |
| 68 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 69 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 70 | |
| 71 | #define EPBAR 0x40 |
| 72 | #define MCHBAR 0x48 |
| 73 | #define PCIEXBAR 0x60 |
| 74 | #define DMIBAR 0x68 |
| 75 | #define X60BAR 0x60 |
| 76 | |
| 77 | #define GGC 0x50 /* GMCH Graphics Control */ |
| 78 | |
| 79 | #define DEVEN 0x54 /* Device Enable */ |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 80 | #define DEVEN_D7EN (1 << 14) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 81 | #define DEVEN_PEG60 (1 << 13) |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 82 | #define DEVEN_D4EN (1 << 7) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 83 | #define DEVEN_IGD (1 << 4) |
| 84 | #define DEVEN_PEG10 (1 << 3) |
| 85 | #define DEVEN_PEG11 (1 << 2) |
| 86 | #define DEVEN_PEG12 (1 << 1) |
| 87 | #define DEVEN_HOST (1 << 0) |
| 88 | |
| 89 | #define PAM0 0x80 |
| 90 | #define PAM1 0x81 |
| 91 | #define PAM2 0x82 |
| 92 | #define PAM3 0x83 |
| 93 | #define PAM4 0x84 |
| 94 | #define PAM5 0x85 |
| 95 | #define PAM6 0x86 |
| 96 | |
| 97 | #define LAC 0x87 /* Legacy Access Control */ |
| 98 | #define SMRAM 0x88 /* System Management RAM Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 99 | |
| 100 | #define TOM 0xa0 |
| 101 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 102 | #define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 103 | #define TSEG 0xb8 /* TSEG base */ |
| 104 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 105 | |
Patrick Rudolph | 9f3f915 | 2016-01-26 20:02:14 +0100 | [diff] [blame] | 106 | #define CAPID0_A 0xe4 /* Capabilities Register A */ |
| 107 | #define CAPID0_B 0xe8 /* Capabilities Register B */ |
| 108 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 109 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 110 | |
| 111 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 112 | |
| 113 | #define BCTRL1 0x3e /* 16bit */ |
| 114 | |
| 115 | |
| 116 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 117 | |
| 118 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * MCHBAR |
| 122 | */ |
| 123 | |
| 124 | #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) |
| 125 | #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) |
| 126 | #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) |
| 127 | #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) |
| 128 | |
| 129 | #define SSKPD 0x5d14 /* 16bit (scratchpad) */ |
| 130 | #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |
| 131 | |
| 132 | /* |
| 133 | * EPBAR - Egress Port Root Complex Register Block |
| 134 | */ |
| 135 | |
| 136 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
| 137 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 138 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 139 | |
| 140 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 141 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 142 | |
| 143 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 144 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 145 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 146 | |
| 147 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 148 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 149 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 150 | |
| 151 | #define EPVC1MTS 0x028 /* 32bit */ |
| 152 | #define EPVC1IST 0x038 /* 64bit */ |
| 153 | |
| 154 | #define EPESD 0x044 /* 32bit */ |
| 155 | |
| 156 | #define EPLE1D 0x050 /* 32bit */ |
| 157 | #define EPLE1A 0x058 /* 64bit */ |
| 158 | #define EPLE2D 0x060 /* 32bit */ |
| 159 | #define EPLE2A 0x068 /* 64bit */ |
| 160 | |
| 161 | #define PORTARB 0x100 /* 256bit */ |
| 162 | |
| 163 | /* |
| 164 | * DMIBAR |
| 165 | */ |
| 166 | |
| 167 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
| 168 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 169 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 170 | |
| 171 | #define DMIVCECH 0x000 /* 32bit */ |
| 172 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 173 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 174 | |
| 175 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 176 | |
| 177 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 178 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 179 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 180 | |
| 181 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 182 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 183 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 184 | |
| 185 | #define DMILE1D 0x050 /* 32bit */ |
| 186 | #define DMILE1A 0x058 /* 64bit */ |
| 187 | #define DMILE2D 0x060 /* 32bit */ |
| 188 | #define DMILE2A 0x068 /* 64bit */ |
| 189 | |
| 190 | #define DMILCAP 0x084 /* 32bit */ |
| 191 | #define DMILCTL 0x088 /* 16bit */ |
| 192 | #define DMILSTS 0x08a /* 16bit */ |
| 193 | |
| 194 | #define DMICTL1 0x0f0 /* 32bit */ |
| 195 | #define DMICTL2 0x0fc /* 32bit */ |
| 196 | |
| 197 | #define DMICC 0x208 /* 32bit */ |
| 198 | |
| 199 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 200 | |
| 201 | #ifndef __ASSEMBLER__ |
| 202 | static inline void barrier(void) { asm("" ::: "memory"); } |
| 203 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 204 | #ifdef __SMM__ |
| 205 | void intel_sandybridge_finalize_smm(void); |
| 206 | #else /* !__SMM__ */ |
| 207 | int bridge_silicon_revision(void); |
| 208 | void sandybridge_early_initialization(int chipset_type); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 209 | void sandybridge_init_iommu(void); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 210 | void sandybridge_late_initialization(void); |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 211 | void northbridge_romstage_finalize(int s3resume); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 212 | |
| 213 | /* debugging functions */ |
| 214 | void print_pci_devices(void); |
| 215 | void dump_pci_device(unsigned dev); |
| 216 | void dump_pci_devices(void); |
| 217 | void dump_spd_registers(void); |
| 218 | void dump_mem(unsigned start, unsigned end); |
Vadim Bendebury | 7a3f36a | 2012-04-18 15:47:32 -0700 | [diff] [blame] | 219 | void report_platform_info(void); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 220 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 221 | #endif /* !__SMM__ */ |
Stefan Reinauer | 1244f4b | 2012-05-10 11:31:40 -0700 | [diff] [blame] | 222 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 223 | void pch_enable_lpc(void); |
| 224 | void mainboard_early_init(int s3resume); |
| 225 | void mainboard_config_superio(void); |
| 226 | int mainboard_should_reset_usb(int s3resume); |
| 227 | void perform_raminit(int s3resume); |
| 228 | |
Antonello Dettori | 6fc430b | 2016-09-02 09:17:26 +0200 | [diff] [blame] | 229 | #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 230 | #include <device/device.h> |
| 231 | |
| 232 | struct acpi_rsdp; |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame^] | 233 | unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 234 | #endif |
| 235 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 236 | #endif |
| 237 | #endif |
Edward O'Callaghan | 089a510 | 2015-01-06 02:48:57 +1100 | [diff] [blame] | 238 | #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ |