| commit | 9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7 | [log] [tgz] |
|---|---|---|
| author | Patrick Rudolph <siro@das-labor.org> | Tue Jan 26 20:02:14 2016 +0100 |
| committer | Martin Roth <martinroth@google.com> | Wed Mar 02 21:46:49 2016 +0100 |
| tree | c473e23fc7dc436629f0ca444ccf113173f632e4 | |
| parent | 2bdeb7f843c707023ea2bd39e314f8eec51c7add [diff] |
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>