nb/intel/sandybridge: Enable basic IOMMU support
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the
integrated graphics controller and one for all other PCI devices. Assign
resources for both IOMMUs and apply some quirks.
Tested with kontron/ktqm77 and a Muen based system that makes use of the
IOMMUs. Not tested on Sandy Bridge, but register dumps show the same
settings that are applied here.
Change-Id: I43b5e20b750e7529f448acac35de173185678fd9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12194
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 506e6fd..853dd1c 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -54,6 +54,9 @@
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
+#define IOMMU_BASE1 0xfed90000ULL
+#define IOMMU_BASE2 0xfed91000ULL
+
#include <southbridge/intel/bd82x6x/pch.h>
/* Everything below this line is ignored in the DSDT */
@@ -199,6 +202,7 @@
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void sandybridge_early_initialization(int chipset_type);
+void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
void northbridge_romstage_finalize(int s3resume);