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review.coreboot.org / coreboot / f4721246db125e08b5e60a8a38a08cb92c478bd3 / . / src / soc / intel / xeon_sp / cpx / Kconfig
blob: 28e7b83386054f2d059993f2e2074003d0107923 [file] [log] [blame]
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]1## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]2
3if SOC_INTEL_COOPERLAKE_SP
4
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]5config FSP_HEADER_PATH
6 string "Location of FSP headers"
7 depends on MAINBOARD_USES_FSP2_0
8 default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
9
10config MAX_SOCKET
11 int
12 default 2
13
14config MAX_CPUS
15 int
Andrey Petrove37d1f72020-04-20 21:11:51 -0700[diff] [blame]16 default 255
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]17
Christian Walter19df8d82020-09-30 13:44:02 +0200[diff] [blame]18config CPU_ADDR_BITS
19 int
20 default 46
21
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]22config PCR_BASE_ADDRESS
23 hex
24 default 0xfd000000
25 help
26 This option allows you to select MMIO Base Address of sideband bus.
27
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]28config DCACHE_RAM_BASE
29 hex
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]30 default 0xfe800000
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]31
32config DCACHE_RAM_SIZE
33 hex
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]34 default 0x1fff00
Jonathan Zhangd4efb332020-07-22 12:39:40 -0700[diff] [blame]35 help
36 The size of the cache-as-ram region required during bootblock
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]37 and/or romstage. FSP-T reserves the upper 0x100 for
38 FspReservedBuffer.
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]39
40config DCACHE_BSP_STACK_SIZE
41 hex
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]42 default 0x140000
Jonathan Zhangd4efb332020-07-22 12:39:40 -0700[diff] [blame]43 help
44 The amount of anticipated stack usage in CAR by bootblock and
45 other stages. It needs to include FSP-M stack requirement and
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]46 CB romstage stack requirement. The integration documentation
47 says this needs to be 256KiB, but practice show this needs to
48 be a lot more.
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]49
50config CPU_MICROCODE_CBFS_LOC
51 hex
52 default 0xfff0fdc0
53
54config CPU_MICROCODE_CBFS_LEN
55 hex
56 default 0x7C00
57
58config C_ENV_BOOTBLOCK_SIZE
59 hex
60 default 0xC000
61
62config HEAP_SIZE
63 hex
64 default 0x80000
65
Jonathan Zhang4337a9a2020-07-31 17:35:25 -0700[diff] [blame]66config STACK_SIZE
67 hex
68 default 0x4000
69
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]70config FSP_TEMP_RAM_SIZE
71 hex
72 depends on FSP_USES_CB_STACK
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]73 default 0x40000
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]74 help
75 The amount of anticipated heap usage in CAR by FSP.
76 Refer to Platform FSP integration guide document to know
Arthur Heymansb38d6bb2020-10-28 18:24:56 +0100[diff] [blame]77 the exact FSP requirement for Heap setup. The FSP integration
78 documentation says this needs to be at least 128KiB, but practice
79 show this needs to be 256KiB or more.
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]80
Andrey Petrovcf270f02020-04-30 13:36:38 -0700[diff] [blame]81config SOC_INTEL_COMMON_BLOCK_P2SB
82 def_bool y
83
Jingle Hsua41b12c2020-08-11 20:48:45 +0800[diff] [blame]84config CPU_BCLK_MHZ
85 int
86 default 100
87
Jonathan Zhangdecf7dc2020-07-27 15:26:30 -0700[diff] [blame]88# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
89# Default value is set to one socket, full config.
90config DIMM_MAX
91 int
92 default 12
93
94# DDR4
95config DIMM_SPD_SIZE
96 int
97 default 512
98
Andrey Petrov2e410752020-03-20 12:08:32 -0700[diff] [blame]99endif