Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 3 | #include <cpu/cpu.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 4 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 6 | #include <acpi/acpigen.h> |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 7 | #include <commonlib/helpers.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <cpu/intel/model_206ax/model_206ax.h> |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 11 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 12 | #include <device/device.h> |
| 13 | #include <device/pci.h> |
| 14 | #include <device/pci_ids.h> |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 15 | #include <types.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 16 | #include "chip.h" |
| 17 | #include "sandybridge.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 18 | #include <cpu/intel/smm_reloc.h> |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 19 | #include <security/intel/txt/txt_platform.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 20 | |
Kyösti Mälkki | f7bfc34 | 2013-10-18 11:02:46 +0300 | [diff] [blame] | 21 | /* IGD UMA memory */ |
| 22 | static uint64_t uma_memory_base = 0; |
| 23 | static uint64_t uma_memory_size = 0; |
| 24 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 25 | bool is_sandybridge(void) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 26 | { |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 27 | const uint16_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); |
| 28 | |
| 29 | return (bridge_id & BASE_REV_MASK) == BASE_REV_SNB; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 30 | } |
| 31 | |
| 32 | /* Reserve everything between A segment and 1MB: |
| 33 | * |
| 34 | * 0xa0000 - 0xbffff: legacy VGA |
| 35 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 36 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 37 | */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 38 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 39 | static const char *northbridge_acpi_name(const struct device *dev) |
| 40 | { |
| 41 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 42 | return "PCI0"; |
| 43 | |
| 44 | if (dev->path.type != DEVICE_PATH_PCI) |
| 45 | return NULL; |
| 46 | |
| 47 | switch (dev->path.pci.devfn) { |
| 48 | case PCI_DEVFN(0, 0): |
| 49 | return "MCHC"; |
| 50 | } |
| 51 | |
| 52 | return NULL; |
| 53 | } |
| 54 | |
Arthur Heymans | fade723 | 2022-11-07 08:47:33 +0100 | [diff] [blame] | 55 | struct device_operations sandybridge_pci_domain_ops = { |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 56 | .read_resources = pci_domain_read_resources, |
| 57 | .set_resources = pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 58 | .scan_bus = pci_host_bridge_scan_bus, |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 59 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 60 | .acpi_name = northbridge_acpi_name, |
| 61 | }; |
| 62 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 63 | static void add_fixed_resources(struct device *dev, int index) |
| 64 | { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 65 | mmio_resource_kb(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | |
Kyösti Mälkki | 8ee11b3 | 2021-06-27 21:08:32 +0300 | [diff] [blame] | 67 | mmio_from_to(dev, index++, 0xa0000, 0xc0000); |
| 68 | reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 69 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 70 | if (is_sandybridge()) { |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 71 | /* Required for SandyBridge sighting 3715511 */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 72 | bad_ram_resource_kb(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |
| 73 | bad_ram_resource_kb(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 74 | } |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 75 | |
| 76 | /* Reserve IOMMU BARs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 77 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 78 | if (!(capid0_a & (1 << 23))) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 79 | mmio_resource_kb(dev, index++, GFXVT_BASE >> 10, 4); |
| 80 | mmio_resource_kb(dev, index++, VTVC0_BASE >> 10, 4); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 81 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 84 | static uint64_t get_touud(const struct device *dev) |
| 85 | { |
| 86 | uint64_t touud = pci_read_config32(dev, TOUUD + 4); |
| 87 | touud <<= 32; |
Arthur Heymans | 1233c43 | 2022-07-29 07:34:03 +0200 | [diff] [blame] | 88 | touud |= pci_read_config32(dev, TOUUD) & 0xfff00000; |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 89 | return touud; |
| 90 | } |
| 91 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 92 | static void mc_read_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 93 | { |
| 94 | uint64_t tom, me_base, touud; |
| 95 | uint32_t tseg_base, uma_size, tolud; |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 96 | uint32_t dpr_base_k, dpr_size_k; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 97 | uint16_t ggc; |
| 98 | unsigned long long tomk; |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 99 | unsigned long index = 3; |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 100 | const union dpr_register dpr = txt_get_chipset_dpr(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 101 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 102 | pci_dev_read_resources(dev); |
| 103 | |
Angel Pons | 10f9b83 | 2021-01-20 14:58:32 +0100 | [diff] [blame] | 104 | mmconf_resource(dev, PCIEXBAR); |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 105 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 106 | /* Total Memory 2GB example: |
| 107 | * |
| 108 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 109 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 110 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 111 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 112 | * 7f200000 2034MB TOLUD |
| 113 | * 7f800000 2040MB MEBASE |
| 114 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 115 | * 80000000 2048MB TOM |
| 116 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 117 | * |
| 118 | * Total Memory 4GB example: |
| 119 | * |
| 120 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 121 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 122 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 123 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 124 | * afa00000 2810MB TOLUD |
| 125 | * ff800000 4088MB MEBASE |
| 126 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 127 | * 100000000 4096MB TOM |
| 128 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 129 | * 14fe00000 5368MB TOUUD |
| 130 | */ |
| 131 | |
| 132 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 133 | touud = get_touud(dev); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 134 | |
| 135 | /* Top of Lower Usable DRAM */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 136 | tolud = pci_read_config32(dev, TOLUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 137 | |
| 138 | /* Top of Memory - does not account for any UMA */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 139 | tom = pci_read_config32(dev, TOM + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 140 | tom <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 141 | tom |= pci_read_config32(dev, TOM); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 142 | |
| 143 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 144 | touud, tolud, tom); |
| 145 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 146 | /* ME UMA needs excluding if total memory < 4GB */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 147 | me_base = pci_read_config32(dev, MESEG_BASE + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 148 | me_base <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 149 | me_base |= pci_read_config32(dev, MESEG_BASE); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 150 | |
| 151 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 152 | |
Patrick Rudolph | 240766a | 2015-10-15 15:33:25 +0200 | [diff] [blame] | 153 | uma_memory_base = tolud; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 154 | tomk = tolud >> 10; |
| 155 | if (me_base == tolud) { |
| 156 | /* ME is from MEBASE-TOM */ |
| 157 | uma_size = (tom - me_base) >> 10; |
| 158 | /* Increment TOLUD to account for ME as RAM */ |
| 159 | tolud += uma_size << 10; |
| 160 | /* UMA starts at old TOLUD */ |
| 161 | uma_memory_base = tomk * 1024ULL; |
| 162 | uma_memory_size = uma_size * 1024ULL; |
| 163 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 164 | me_base, uma_size >> 10); |
| 165 | } |
| 166 | |
| 167 | /* Graphics memory comes next */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 168 | ggc = pci_read_config16(dev, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 169 | if (!(ggc & 2)) { |
| 170 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 171 | |
| 172 | /* Graphics memory */ |
| 173 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 174 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 175 | tomk -= uma_size; |
| 176 | uma_memory_base = tomk * 1024ULL; |
| 177 | uma_memory_size += uma_size * 1024ULL; |
| 178 | |
| 179 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 180 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 181 | tomk -= uma_size; |
| 182 | uma_memory_base = tomk * 1024ULL; |
| 183 | uma_memory_size += uma_size * 1024ULL; |
| 184 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 185 | } |
| 186 | |
| 187 | /* Calculate TSEG size from its base which must be below GTT */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 188 | tseg_base = pci_read_config32(dev, TSEGMB); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 189 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 190 | tomk -= uma_size; |
| 191 | uma_memory_base = tomk * 1024ULL; |
| 192 | uma_memory_size += uma_size * 1024ULL; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 193 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 194 | |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 195 | /* Calculate DMA Protected Region if enabled */ |
| 196 | if (dpr.epm && dpr.size) { |
| 197 | dpr_size_k = dpr.size * MiB / KiB; |
| 198 | tomk -= dpr_size_k; |
| 199 | dpr_base_k = (tseg_base - dpr.size * MiB) / KiB; |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 200 | reserved_ram_resource_kb(dev, index++, dpr_base_k, dpr_size_k); |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 201 | printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size); |
| 202 | } |
| 203 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 204 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 205 | |
| 206 | /* Report the memory regions */ |
Kyösti Mälkki | 8ee11b3 | 2021-06-27 21:08:32 +0300 | [diff] [blame] | 207 | ram_from_to(dev, index++, 0, 0xa0000); |
| 208 | ram_from_to(dev, index++, 1 * MiB, tomk * KiB); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 209 | |
| 210 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 211 | * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. |
| 212 | * TOUUD will account for both memory chunks. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 213 | */ |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 214 | upper_ram_end(dev, index++, touud); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 215 | |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 216 | add_fixed_resources(dev, index++); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 217 | } |
| 218 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 219 | static void northbridge_dmi_init(struct device *dev) |
| 220 | { |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 221 | const bool is_sandy = is_sandybridge(); |
| 222 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 223 | const u8 stepping = cpu_stepping(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 224 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 225 | /* Steps prior to DMI ASPM */ |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 226 | if (is_sandy) { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 227 | dmibar_clrsetbits32(0x250, 7 << 20, 2 << 20); |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 228 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 229 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 230 | dmibar_setbits32(DMILLTC, 1 << 29); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 231 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 232 | if (is_sandy && stepping == SNB_STEP_C0) { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 233 | dmibar_clrsetbits32(0xbc8, 0xfff << 7, 0x7d3 << 7); |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 234 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 235 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 236 | if (!is_sandy || stepping >= SNB_STEP_D1) { |
Angel Pons | 0acfe22 | 2021-03-26 13:08:23 +0100 | [diff] [blame] | 237 | dmibar_clrsetbits32(0x1f8, 1 << 26, 1 << 16); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 238 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 239 | dmibar_setbits32(0x1fc, 1 << 12 | 1 << 23); |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 240 | |
| 241 | } else if (stepping >= SNB_STEP_D0) { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 242 | dmibar_setbits32(0x1f8, 1 << 16); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 243 | } |
| 244 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 245 | /* Clear error status bits */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 246 | dmibar_write32(DMIUESTS, 0xffffffff); |
| 247 | dmibar_write32(DMICESTS, 0xffffffff); |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 248 | |
| 249 | if (!is_sandy) |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 250 | dmibar_write32(0xc34, 0xffffffff); |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 251 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 252 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 253 | if (is_sandy) { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 254 | dmibar_setbits32(0xd04, 1 << 4); |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 255 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 256 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 257 | dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 258 | } |
| 259 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 260 | /* Disable unused PEG devices based on devicetree */ |
| 261 | static void disable_peg(void) |
| 262 | { |
| 263 | struct device *dev; |
| 264 | u32 reg; |
| 265 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 266 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 267 | reg = pci_read_config32(dev, DEVEN); |
| 268 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 269 | dev = pcidev_on_root(1, 2); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 270 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 271 | printk(BIOS_DEBUG, "Disabling PEG12.\n"); |
| 272 | reg &= ~DEVEN_PEG12; |
| 273 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 274 | dev = pcidev_on_root(1, 1); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 275 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 276 | printk(BIOS_DEBUG, "Disabling PEG11.\n"); |
| 277 | reg &= ~DEVEN_PEG11; |
| 278 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 279 | dev = pcidev_on_root(1, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 280 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 281 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 282 | reg &= ~DEVEN_PEG10; |
| 283 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 284 | dev = pcidev_on_root(2, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 285 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 286 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 287 | reg &= ~DEVEN_IGD; |
| 288 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 289 | dev = pcidev_on_root(4, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 290 | if (!dev || !dev->enabled) { |
| 291 | printk(BIOS_DEBUG, "Disabling Device 4.\n"); |
| 292 | reg &= ~DEVEN_D4EN; |
| 293 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 294 | dev = pcidev_on_root(6, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 295 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 296 | printk(BIOS_DEBUG, "Disabling PEG60.\n"); |
| 297 | reg &= ~DEVEN_PEG60; |
| 298 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 299 | dev = pcidev_on_root(7, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 300 | if (!dev || !dev->enabled) { |
| 301 | printk(BIOS_DEBUG, "Disabling Device 7.\n"); |
| 302 | reg &= ~DEVEN_D7EN; |
| 303 | } |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 304 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 305 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 306 | pci_write_config32(dev, DEVEN, reg); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 307 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 308 | if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 309 | /* |
| 310 | * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. |
| 311 | * |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 312 | * FIXME: Never clock gate on Ivy Bridge stepping A0! |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 313 | */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 314 | mchbar_setbits32(PEGCTL, 1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 315 | printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 316 | } else { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 317 | mchbar_clrbits32(PEGCTL, 1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 318 | } |
| 319 | } |
| 320 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 321 | static void northbridge_init(struct device *dev) |
| 322 | { |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 323 | u32 bridge_type; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 324 | |
| 325 | northbridge_dmi_init(dev); |
| 326 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 327 | bridge_type = mchbar_read32(SAPMTIMERS); |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 328 | bridge_type &= ~0xff; |
| 329 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 330 | if (is_sandybridge()) { |
| 331 | /* 20h for Sandybridge */ |
| 332 | bridge_type |= 0x20; |
| 333 | } else { |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 334 | /* Enable Power Aware Interrupt Routing */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 335 | mchbar_clrsetbits8(INTRDIRCTL, 0xf, 0x4); /* Clear 3:0, set Fixed Priority */ |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 336 | |
| 337 | /* 30h for IvyBridge */ |
| 338 | bridge_type |= 0x30; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 339 | } |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 340 | mchbar_write32(SAPMTIMERS, bridge_type); |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 341 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 342 | /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ |
Patrick Rudolph | aad34cd | 2015-10-21 18:05:01 +0200 | [diff] [blame] | 343 | disable_peg(); |
| 344 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 345 | /* |
| 346 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 347 | * that BIOS has initialized memory and power management |
| 348 | */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 349 | mchbar_setbits8(BIOS_RESET_CPL, 1 << 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 350 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 351 | |
| 352 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 353 | mdelay(1); |
| 354 | set_power_limits(28); |
| 355 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 356 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 357 | * CPUs with configurable TDP also need power limits set in MCHBAR. |
| 358 | * Use the same values from MSR_PKG_POWER_LIMIT. |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 359 | */ |
| 360 | if (cpu_config_tdp_levels()) { |
| 361 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 362 | mchbar_write32(MCH_PKG_POWER_LIMIT_LO, msr.lo); |
| 363 | mchbar_write32(MCH_PKG_POWER_LIMIT_HI, msr.hi); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 364 | } |
| 365 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 366 | /* Set here before graphics PM init */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 367 | mchbar_write32(PAVP_MSG, 0x00100001); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 368 | } |
| 369 | |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 370 | void northbridge_write_smram(u8 smram) |
| 371 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 372 | pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 373 | } |
| 374 | |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 375 | static void set_above_4g_pci(const struct device *dev) |
| 376 | { |
| 377 | const uint64_t touud = get_touud(dev); |
| 378 | const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; |
| 379 | |
| 380 | acpigen_write_scope("\\"); |
| 381 | acpigen_write_name_qword("A4GB", touud); |
| 382 | acpigen_write_name_qword("A4GS", len); |
| 383 | acpigen_pop_len(); |
| 384 | |
| 385 | printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); |
| 386 | } |
| 387 | |
| 388 | static void mc_gen_ssdt(const struct device *dev) |
| 389 | { |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 390 | set_above_4g_pci(dev); |
| 391 | } |
| 392 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 393 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 394 | .read_resources = mc_read_resources, |
| 395 | .set_resources = pci_dev_set_resources, |
| 396 | .enable_resources = pci_dev_enable_resources, |
| 397 | .init = northbridge_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 398 | .ops_pci = &pci_dev_ops_pci, |
Arthur Heymans | f8daf86 | 2021-02-24 19:21:33 +0100 | [diff] [blame] | 399 | .acpi_fill_ssdt = mc_gen_ssdt, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 400 | }; |
| 401 | |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 402 | static const unsigned short pci_device_ids[] = { |
Jonathan A. Kollasch | d346a19 | 2020-02-11 09:03:48 -0600 | [diff] [blame] | 403 | 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 404 | 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ |
| 405 | 0 |
Walter Murphy | 496f4a0 | 2012-04-23 11:08:03 -0700 | [diff] [blame] | 406 | }; |
| 407 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 408 | static const struct pci_driver mc_driver __pci_driver = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 409 | .ops = &mc_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 410 | .vendor = PCI_VID_INTEL, |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 411 | .devices = pci_device_ids, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 412 | }; |
| 413 | |
Arthur Heymans | fade723 | 2022-11-07 08:47:33 +0100 | [diff] [blame] | 414 | struct device_operations sandybridge_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 415 | .read_resources = noop_read_resources, |
| 416 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 417 | .init = mp_cpu_bus_init, |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 418 | .acpi_fill_ssdt = generate_cpu_entries, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 419 | }; |
| 420 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 421 | struct chip_operations northbridge_intel_sandybridge_ops = { |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 422 | CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 423 | }; |