| commit | 1233c43a983f0e05cf19c670b790d5e0fe66e2af | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Fri Jul 29 07:34:03 2022 +0200 |
| committer | Arthur Heymans <arthur@aheymans.xyz> | Fri Aug 26 14:20:26 2022 +0000 |
| tree | 0791bee4d74de6212d93b0c74e1a7ad77dc71e03 | |
| parent | 5436548993d465d55169c91b2acfd46b3287ec95 [diff] [blame] |
nb/intel/sandybridge: Align TOUUD down to 1 MiB granularity This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 14fde8b0..521044b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -85,7 +85,7 @@ { uint64_t touud = pci_read_config32(dev, TOUUD + 4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= pci_read_config32(dev, TOUUD) & 0xfff00000; return touud; }