Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame^] | 5 | #include <acpi/acpi.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <delay.h> |
| 9 | #include <cpu/intel/model_206ax/model_206ax.h> |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | #include "sandybridge.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 17 | |
| 18 | static int bridge_revision_id = -1; |
| 19 | |
Kyösti Mälkki | f7bfc34 | 2013-10-18 11:02:46 +0300 | [diff] [blame] | 20 | /* IGD UMA memory */ |
| 21 | static uint64_t uma_memory_base = 0; |
| 22 | static uint64_t uma_memory_size = 0; |
| 23 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | int bridge_silicon_revision(void) |
| 25 | { |
| 26 | if (bridge_revision_id < 0) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 27 | uint8_t stepping = cpuid_eax(1) & 0x0f; |
| 28 | uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); |
| 29 | bridge_revision_id = (bridge_id & 0xf0) | stepping; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 30 | } |
| 31 | return bridge_revision_id; |
| 32 | } |
| 33 | |
| 34 | /* Reserve everything between A segment and 1MB: |
| 35 | * |
| 36 | * 0xa0000 - 0xbffff: legacy VGA |
| 37 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 38 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 39 | */ |
| 40 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 41 | static const int legacy_hole_size_k = 384; |
| 42 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 43 | static int get_pcie_bar(u32 *base) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 44 | { |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 45 | struct device *dev; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 46 | u32 pciexbar_reg; |
| 47 | |
| 48 | *base = 0; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 49 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 50 | dev = pcidev_on_root(0, 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 51 | if (!dev) |
| 52 | return 0; |
| 53 | |
| 54 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
| 55 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 56 | /* MMCFG not supported or not enabled */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 57 | if (!(pciexbar_reg & (1 << 0))) |
| 58 | return 0; |
| 59 | |
| 60 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 61 | case 0: /* 256MB */ |
| 62 | *base = pciexbar_reg & (0xffffffffULL << 28); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 63 | return 256; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 64 | case 1: /* 128M */ |
| 65 | *base = pciexbar_reg & (0xffffffffULL << 27); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 66 | return 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 67 | case 2: /* 64M */ |
| 68 | *base = pciexbar_reg & (0xffffffffULL << 26); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 69 | return 64; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 75 | static void add_fixed_resources(struct device *dev, int index) |
| 76 | { |
Kyösti Mälkki | 7f189cc | 2012-07-27 13:12:03 +0300 | [diff] [blame] | 77 | mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 78 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 79 | mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); |
| 80 | |
| 81 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 82 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 83 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 84 | reserved_ram_resource(dev, index++, |
| 85 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 86 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 87 | #endif |
| 88 | |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 89 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 90 | /* Required for SandyBridge sighting 3715511 */ |
| 91 | bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |
| 92 | bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); |
| 93 | } |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 94 | |
| 95 | /* Reserve IOMMU BARs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 96 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 97 | if (!(capid0_a & (1 << 23))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 98 | mmio_resource(dev, index++, GFXVT_BASE >> 10, 4); |
| 99 | mmio_resource(dev, index++, VTVC0_BASE >> 10, 4); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 100 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 101 | } |
| 102 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 103 | static void pci_domain_set_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 104 | { |
| 105 | uint64_t tom, me_base, touud; |
| 106 | uint32_t tseg_base, uma_size, tolud; |
| 107 | uint16_t ggc; |
| 108 | unsigned long long tomk; |
| 109 | |
| 110 | /* Total Memory 2GB example: |
| 111 | * |
| 112 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 113 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 114 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 115 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 116 | * 7f200000 2034MB TOLUD |
| 117 | * 7f800000 2040MB MEBASE |
| 118 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 119 | * 80000000 2048MB TOM |
| 120 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 121 | * |
| 122 | * Total Memory 4GB example: |
| 123 | * |
| 124 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 125 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 126 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 127 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 128 | * afa00000 2810MB TOLUD |
| 129 | * ff800000 4088MB MEBASE |
| 130 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 131 | * 100000000 4096MB TOM |
| 132 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 133 | * 14fe00000 5368MB TOUUD |
| 134 | */ |
| 135 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 136 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 137 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 138 | /* Top of Upper Usable DRAM, including remap */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 139 | touud = pci_read_config32(mch, TOUUD + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 140 | touud <<= 32; |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 141 | touud |= pci_read_config32(mch, TOUUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 142 | |
| 143 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 144 | tolud = pci_read_config32(mch, TOLUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 145 | |
| 146 | /* Top of Memory - does not account for any UMA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 147 | tom = pci_read_config32(mch, TOM + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 148 | tom <<= 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 149 | tom |= pci_read_config32(mch, TOM); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 150 | |
| 151 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 152 | touud, tolud, tom); |
| 153 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 154 | /* ME UMA needs excluding if total memory < 4GB */ |
| 155 | me_base = pci_read_config32(mch, MESEG_BASE + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 156 | me_base <<= 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 157 | me_base |= pci_read_config32(mch, MESEG_BASE); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 158 | |
| 159 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 160 | |
Patrick Rudolph | 240766a | 2015-10-15 15:33:25 +0200 | [diff] [blame] | 161 | uma_memory_base = tolud; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 162 | tomk = tolud >> 10; |
| 163 | if (me_base == tolud) { |
| 164 | /* ME is from MEBASE-TOM */ |
| 165 | uma_size = (tom - me_base) >> 10; |
| 166 | /* Increment TOLUD to account for ME as RAM */ |
| 167 | tolud += uma_size << 10; |
| 168 | /* UMA starts at old TOLUD */ |
| 169 | uma_memory_base = tomk * 1024ULL; |
| 170 | uma_memory_size = uma_size * 1024ULL; |
| 171 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 172 | me_base, uma_size >> 10); |
| 173 | } |
| 174 | |
| 175 | /* Graphics memory comes next */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 176 | ggc = pci_read_config16(mch, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 177 | if (!(ggc & 2)) { |
| 178 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 179 | |
| 180 | /* Graphics memory */ |
| 181 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 182 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 183 | tomk -= uma_size; |
| 184 | uma_memory_base = tomk * 1024ULL; |
| 185 | uma_memory_size += uma_size * 1024ULL; |
| 186 | |
| 187 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 188 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 189 | tomk -= uma_size; |
| 190 | uma_memory_base = tomk * 1024ULL; |
| 191 | uma_memory_size += uma_size * 1024ULL; |
| 192 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 193 | } |
| 194 | |
| 195 | /* Calculate TSEG size from its base which must be below GTT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 196 | tseg_base = pci_read_config32(mch, TSEGMB); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 197 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 198 | tomk -= uma_size; |
| 199 | uma_memory_base = tomk * 1024ULL; |
| 200 | uma_memory_size += uma_size * 1024ULL; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 201 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 202 | |
| 203 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 204 | |
| 205 | /* Report the memory regions */ |
| 206 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 207 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 208 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 209 | |
| 210 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 211 | * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. |
| 212 | * TOUUD will account for both memory chunks. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 213 | */ |
| 214 | touud >>= 10; /* Convert to KB */ |
| 215 | if (touud > 4096 * 1024) { |
| 216 | ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 217 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | add_fixed_resources(dev, 6); |
| 221 | |
| 222 | assign_resources(dev->link_list); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 223 | } |
| 224 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 225 | static const char *northbridge_acpi_name(const struct device *dev) |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 226 | { |
| 227 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 228 | return "PCI0"; |
| 229 | |
| 230 | if (dev->path.type != DEVICE_PATH_PCI) |
| 231 | return NULL; |
| 232 | |
| 233 | switch (dev->path.pci.devfn) { |
| 234 | case PCI_DEVFN(0, 0): |
| 235 | return "MCHC"; |
| 236 | } |
| 237 | |
| 238 | return NULL; |
| 239 | } |
| 240 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 241 | /* |
| 242 | * TODO We could determine how many PCIe busses we need in the bar. |
| 243 | * For now, that number is hardcoded to a max of 64. |
| 244 | */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 245 | static struct device_operations pci_domain_ops = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 246 | .read_resources = pci_domain_read_resources, |
| 247 | .set_resources = pci_domain_set_resources, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 248 | .scan_bus = pci_domain_scan_bus, |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 249 | .write_acpi_tables = northbridge_write_acpi_tables, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 250 | .acpi_name = northbridge_acpi_name, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 251 | }; |
| 252 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 253 | static void mc_read_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 254 | { |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 255 | u32 pcie_config_base; |
| 256 | int buses; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 257 | |
| 258 | pci_dev_read_resources(dev); |
| 259 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 260 | buses = get_pcie_bar(&pcie_config_base); |
| 261 | if (buses) { |
Kyösti Mälkki | 27198ac | 2016-12-02 14:38:13 +0200 | [diff] [blame] | 262 | struct resource *resource = new_resource(dev, PCIEXBAR); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 263 | mmconf_resource_init(resource, pcie_config_base, buses); |
| 264 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 265 | } |
| 266 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 267 | static void northbridge_dmi_init(struct device *dev) |
| 268 | { |
| 269 | u32 reg32; |
| 270 | |
| 271 | /* Clear error status bits */ |
| 272 | DMIBAR32(0x1c4) = 0xffffffff; |
| 273 | DMIBAR32(0x1d0) = 0xffffffff; |
| 274 | |
| 275 | /* Steps prior to DMI ASPM */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 276 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 277 | reg32 = DMIBAR32(0x250); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 278 | reg32 &= ~((1 << 22) | (1 << 20)); |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 279 | reg32 |= (1 << 21); |
| 280 | DMIBAR32(0x250) = reg32; |
| 281 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 282 | |
| 283 | reg32 = DMIBAR32(0x238); |
| 284 | reg32 |= (1 << 29); |
| 285 | DMIBAR32(0x238) = reg32; |
| 286 | |
| 287 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 288 | reg32 = DMIBAR32(0x1f8); |
| 289 | reg32 |= (1 << 16); |
| 290 | DMIBAR32(0x1f8) = reg32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 291 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 292 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 293 | reg32 = DMIBAR32(0x1f8); |
| 294 | reg32 &= ~(1 << 26); |
| 295 | reg32 |= (1 << 16); |
| 296 | DMIBAR32(0x1f8) = reg32; |
| 297 | |
| 298 | reg32 = DMIBAR32(0x1fc); |
| 299 | reg32 |= (1 << 12) | (1 << 23); |
| 300 | DMIBAR32(0x1fc) = reg32; |
| 301 | } |
| 302 | |
| 303 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 304 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 305 | reg32 = DMIBAR32(0xd04); |
| 306 | reg32 |= (1 << 4); |
| 307 | DMIBAR32(0xd04) = reg32; |
| 308 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 309 | |
| 310 | reg32 = DMIBAR32(0x88); |
| 311 | reg32 |= (1 << 1) | (1 << 0); |
| 312 | DMIBAR32(0x88) = reg32; |
| 313 | } |
| 314 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 315 | /* Disable unused PEG devices based on devicetree */ |
| 316 | static void disable_peg(void) |
| 317 | { |
| 318 | struct device *dev; |
| 319 | u32 reg; |
| 320 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 321 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 322 | reg = pci_read_config32(dev, DEVEN); |
| 323 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 324 | dev = pcidev_on_root(1, 2); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 325 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 326 | printk(BIOS_DEBUG, "Disabling PEG12.\n"); |
| 327 | reg &= ~DEVEN_PEG12; |
| 328 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 329 | dev = pcidev_on_root(1, 1); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 330 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 331 | printk(BIOS_DEBUG, "Disabling PEG11.\n"); |
| 332 | reg &= ~DEVEN_PEG11; |
| 333 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 334 | dev = pcidev_on_root(1, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 335 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 336 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 337 | reg &= ~DEVEN_PEG10; |
| 338 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 339 | dev = pcidev_on_root(2, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 340 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 341 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 342 | reg &= ~DEVEN_IGD; |
| 343 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 344 | dev = pcidev_on_root(4, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 345 | if (!dev || !dev->enabled) { |
| 346 | printk(BIOS_DEBUG, "Disabling Device 4.\n"); |
| 347 | reg &= ~DEVEN_D4EN; |
| 348 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 349 | dev = pcidev_on_root(6, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 350 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 351 | printk(BIOS_DEBUG, "Disabling PEG60.\n"); |
| 352 | reg &= ~DEVEN_PEG60; |
| 353 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 354 | dev = pcidev_on_root(7, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 355 | if (!dev || !dev->enabled) { |
| 356 | printk(BIOS_DEBUG, "Disabling Device 7.\n"); |
| 357 | reg &= ~DEVEN_D7EN; |
| 358 | } |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 359 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 360 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 361 | pci_write_config32(dev, DEVEN, reg); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 362 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 363 | if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 364 | /* |
| 365 | * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. |
| 366 | * |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 367 | * FIXME: Never clock gate on Ivy Bridge stepping A0! |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 368 | */ |
| 369 | MCHBAR32_OR(PEGCTL, 1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 370 | printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 371 | } else { |
| 372 | MCHBAR32_AND(PEGCTL, ~1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 373 | } |
| 374 | } |
| 375 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 376 | static void northbridge_init(struct device *dev) |
| 377 | { |
| 378 | u8 bios_reset_cpl; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 379 | u32 bridge_type; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 380 | |
| 381 | northbridge_dmi_init(dev); |
| 382 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 383 | bridge_type = MCHBAR32(SAPMTIMERS); |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 384 | bridge_type &= ~0xff; |
| 385 | |
| 386 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 387 | /* Enable Power Aware Interrupt Routing */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 388 | u8 pair = MCHBAR8(INTRDIRCTL); |
| 389 | pair &= ~0x0f; /* Clear 3:0 */ |
| 390 | pair |= 0x04; /* Fixed Priority */ |
| 391 | MCHBAR8(INTRDIRCTL) = pair; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 392 | |
| 393 | /* 30h for IvyBridge */ |
| 394 | bridge_type |= 0x30; |
| 395 | } else { |
| 396 | /* 20h for Sandybridge */ |
| 397 | bridge_type |= 0x20; |
| 398 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 399 | MCHBAR32(SAPMTIMERS) = bridge_type; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 400 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 401 | /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ |
Patrick Rudolph | aad34cd | 2015-10-21 18:05:01 +0200 | [diff] [blame] | 402 | disable_peg(); |
| 403 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 404 | /* |
| 405 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 406 | * that BIOS has initialized memory and power management |
| 407 | */ |
| 408 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 409 | bios_reset_cpl |= 1; |
| 410 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 411 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 412 | |
| 413 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 414 | mdelay(1); |
| 415 | set_power_limits(28); |
| 416 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 417 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 418 | * CPUs with configurable TDP also need power limits set in MCHBAR. |
| 419 | * Use the same values from MSR_PKG_POWER_LIMIT. |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 420 | */ |
| 421 | if (cpu_config_tdp_levels()) { |
| 422 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 423 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo; |
| 424 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi; |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 425 | } |
| 426 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 427 | /* Set here before graphics PM init */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 428 | MCHBAR32(PAVP_MSG) = 0x00100001; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 429 | } |
| 430 | |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 431 | void northbridge_write_smram(u8 smram) |
| 432 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 433 | pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 434 | } |
| 435 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 436 | static struct pci_operations intel_pci_ops = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 437 | .set_subsystem = pci_dev_set_subsystem, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 441 | .read_resources = mc_read_resources, |
| 442 | .set_resources = pci_dev_set_resources, |
| 443 | .enable_resources = pci_dev_enable_resources, |
| 444 | .init = northbridge_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 445 | .ops_pci = &intel_pci_ops, |
| 446 | .acpi_fill_ssdt = generate_cpu_entries, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 447 | }; |
| 448 | |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 449 | static const unsigned short pci_device_ids[] = { |
Jonathan A. Kollasch | d346a19 | 2020-02-11 09:03:48 -0600 | [diff] [blame] | 450 | 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 451 | 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ |
| 452 | 0 |
Walter Murphy | 496f4a0 | 2012-04-23 11:08:03 -0700 | [diff] [blame] | 453 | }; |
| 454 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 455 | static const struct pci_driver mc_driver __pci_driver = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 456 | .ops = &mc_ops, |
| 457 | .vendor = PCI_VENDOR_ID_INTEL, |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 458 | .devices = pci_device_ids, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 459 | }; |
| 460 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 461 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 462 | .read_resources = noop_read_resources, |
| 463 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 464 | .init = mp_cpu_bus_init, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 465 | }; |
| 466 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 467 | static void enable_dev(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 468 | { |
| 469 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 470 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 471 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 472 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 473 | dev->ops = &cpu_bus_ops; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | struct chip_operations northbridge_intel_sandybridge_ops = { |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 478 | CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 479 | .enable_dev = enable_dev, |
| 480 | }; |