commit 77516ca79225f91fdcb4fc837f141a320de5371a
author Angel Pons <th3fanbus@gmail.com> Thu Dec 10 16:43:25 2020 +0100
committer Patrick Georgi <pgeorgi@google.com> Mon Jan 25 09:07:24 2021 +0000
tree 3d86f48fe275f786872e0094c921b6a680879d64
parent e515515e2e02575972b487a2dc2dd5b779ebf370

nb/intel/sandybridge: Correct late DMI init sequence

Based on reference code, update the DMI ASPM setup steps.

Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/sandybridge/northbridge.c

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 4d87878..dc1be32 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -256,17 +256,15 @@
 {
 	const bool is_sandy = is_sandybridge();
 
-	u32 reg32;
+	const u8 stepping = cpu_stepping();
 
-	/* Clear error status bits */
-	DMIBAR32(DMIUESTS) = 0xffffffff;
-	DMIBAR32(DMICESTS) = 0xffffffff;
+	u32 reg32;
 
 	/* Steps prior to DMI ASPM */
 	if (is_sandy) {
 		reg32 = DMIBAR32(0x250);
-		reg32 &= ~((1 << 22) | (1 << 20));
-		reg32 |= (1 << 21);
+		reg32 &= ~(7 << 20);
+		reg32 |= (2 << 20);
 		DMIBAR32(0x250) = reg32;
 	}
 
@@ -274,12 +272,14 @@
 	reg32 |= (1 << 29);
 	DMIBAR32(DMILLTC) = reg32;
 
-	if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) {
-		reg32 = DMIBAR32(0x1f8);
-		reg32 |= (1 << 16);
-		DMIBAR32(0x1f8) = reg32;
+	if (is_sandy && stepping == SNB_STEP_C0) {
+		reg32 = DMIBAR32(0xbc8);
+		reg32 &= ~(0xfff << 7);
+		reg32 |= (0x7d3 << 7);
+		DMIBAR32(0xbc8) = reg32;
+	}
 
-	} else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) {
+	if (!is_sandy || stepping >= SNB_STEP_D1) {
 		reg32 = DMIBAR32(0x1f8);
 		reg32 &= ~(1 << 26);
 		reg32 |= (1 << 16);
@@ -288,8 +288,20 @@
 		reg32 = DMIBAR32(0x1fc);
 		reg32 |= (1 << 12) | (1 << 23);
 		DMIBAR32(0x1fc) = reg32;
+
+	} else if (stepping >= SNB_STEP_D0) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
 	}
 
+	/* Clear error status bits */
+	DMIBAR32(DMIUESTS) = 0xffffffff;
+	DMIBAR32(DMICESTS) = 0xffffffff;
+
+	if (!is_sandy)
+		DMIBAR32(0xc34) = 0xffffffff;
+
 	/* Enable ASPM on SNB link, should happen before PCH link */
 	if (is_sandy) {
 		reg32 = DMIBAR32(0xd04);