commit 0ff99b70f5c5b6797507d3f152c5d452e1210110
author Vincent Palatin <vpalatin@chromium.org> Wed Mar 28 16:10:29 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue May 01 20:04:24 2012 +0200
tree 32345e23a3e71ce520b5cd6fd8dfa87fcfff0de4
parent 459b7777fe871c5c9bd6636b1b13efc784129e31

Modify DMI init for IvyBridge

The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.

Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/northbridge/intel/sandybridge/northbridge.c

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index e3334c4..b1f7c72 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -347,10 +347,12 @@
 	DMIBAR32(0x1d0) = 0xffffffff;
 
 	/* Steps prior to DMI ASPM */
-	reg32 = DMIBAR32(0x250);
-	reg32 &= ~((1 << 22)|(1 << 20));
-	reg32 |= (1 << 21);
-	DMIBAR32(0x250) = reg32;
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0x250);
+		reg32 &= ~((1 << 22)|(1 << 20));
+		reg32 |= (1 << 21);
+		DMIBAR32(0x250) = reg32;
+	}
 
 	reg32 = DMIBAR32(0x238);
 	reg32 |= (1 << 29);
@@ -372,9 +374,11 @@
 	}
 
 	/* Enable ASPM on SNB link, should happen before PCH link */
-	reg32 = DMIBAR32(0xd04);
-	reg32 |= (1 << 4);
-	DMIBAR32(0xd04) = reg32;
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0xd04);
+		reg32 |= (1 << 4);
+		DMIBAR32(0xd04) = reg32;
+	}
 
 	reg32 = DMIBAR32(0x88);
 	reg32 |= (1 << 1) | (1 << 0);