Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 1366e44 | 2020-09-29 13:55:50 +0530 | [diff] [blame] | 5 | #include <arch/ioapic.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 6 | #include <assert.h> |
| 7 | #include <console/console.h> |
| 8 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Subrata Banik | 78463a7 | 2020-09-29 14:28:09 +0530 | [diff] [blame] | 10 | #include <intelblocks/itss.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 11 | #include <intelblocks/lpc_lib.h> |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 12 | #include <intelblocks/pcr.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 13 | #include <lib.h> |
| 14 | #include "lpc_def.h" |
Subrata Banik | 78463a7 | 2020-09-29 14:28:09 +0530 | [diff] [blame] | 15 | #include <soc/irq.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 17 | #include <soc/pcr_ids.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 18 | |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 19 | uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 20 | { |
| 21 | uint16_t reg_io_enables; |
| 22 | |
| 23 | reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); |
| 24 | io_enables |= reg_io_enables; |
| 25 | pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 26 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) |
| 27 | pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 28 | |
| 29 | return io_enables; |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 30 | } |
| 31 | |
Wim Vervoorn | e6db910 | 2020-02-03 14:57:40 +0100 | [diff] [blame] | 32 | uint16_t lpc_get_fixed_io_decode(void) |
| 33 | { |
| 34 | return pci_read_config16(PCH_DEV_LPC, LPC_IO_DECODE); |
| 35 | } |
| 36 | |
Wim Vervoorn | 5f2adfe | 2020-02-03 15:32:54 +0100 | [diff] [blame] | 37 | uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask) |
| 38 | { |
| 39 | uint16_t reg_io_ranges; |
| 40 | |
| 41 | reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; |
| 42 | io_ranges |= reg_io_ranges & mask; |
| 43 | pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 44 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) |
| 45 | pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); |
Wim Vervoorn | 5f2adfe | 2020-02-03 15:32:54 +0100 | [diff] [blame] | 46 | |
| 47 | return io_ranges; |
| 48 | } |
| 49 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 50 | /* |
| 51 | * Find the first unused IO window. |
| 52 | * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... |
| 53 | */ |
| 54 | static int find_unused_pmio_window(void) |
| 55 | { |
| 56 | int i; |
| 57 | uint32_t lgir; |
| 58 | |
| 59 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { |
| 60 | lgir = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i)); |
| 61 | |
| 62 | if (!(lgir & LPC_LGIR_EN)) |
| 63 | return i; |
| 64 | } |
| 65 | |
| 66 | return -1; |
| 67 | } |
| 68 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 69 | void lpc_open_pmio_window(uint16_t base, uint16_t size) |
| 70 | { |
Lijian Zhao | e6db189 | 2018-04-13 16:27:38 -0700 | [diff] [blame] | 71 | int i, lgir_reg_num; |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 72 | uint32_t lgir_reg_offset, lgir, window_size, alignment; |
| 73 | resource_t bridged_size, bridge_base; |
| 74 | |
| 75 | printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n", |
| 76 | base, size); |
| 77 | |
| 78 | bridged_size = 0; |
| 79 | bridge_base = base; |
| 80 | |
| 81 | while (bridged_size < size) { |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 82 | /* Each IO range register can only open a 256-byte window. */ |
| 83 | window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); |
| 84 | |
John Zhao | 1ceac4e | 2019-07-09 14:27:28 -0700 | [diff] [blame] | 85 | if (window_size <= 0) |
John Zhao | 2bb432e | 2019-05-21 19:32:51 -0700 | [diff] [blame] | 86 | return; |
| 87 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 88 | /* Window size must be a power of two for the AMASK to work. */ |
Paul Menzel | fa7d2a0 | 2017-10-27 15:54:26 +0200 | [diff] [blame] | 89 | alignment = 1UL << (log2_ceil(window_size)); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 90 | window_size = ALIGN_UP(window_size, alignment); |
| 91 | |
| 92 | /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18]. */ |
| 93 | lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN; |
| 94 | lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; |
| 95 | |
Lijian Zhao | e6db189 | 2018-04-13 16:27:38 -0700 | [diff] [blame] | 96 | /* Skip programming if same range already programmed. */ |
| 97 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { |
| 98 | if (lgir == pci_read_config32(PCH_DEV_LPC, |
| 99 | LPC_GENERIC_IO_RANGE(i))) |
| 100 | return; |
| 101 | } |
| 102 | |
| 103 | lgir_reg_num = find_unused_pmio_window(); |
| 104 | if (lgir_reg_num < 0) { |
| 105 | printk(BIOS_ERR, |
| 106 | "LPC: Cannot open IO window: %llx size %llx\n", |
| 107 | bridge_base, size - bridged_size); |
| 108 | printk(BIOS_ERR, "No more IO windows\n"); |
| 109 | return; |
| 110 | } |
| 111 | lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); |
| 112 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 113 | pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 114 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) |
| 115 | pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 116 | |
| 117 | printk(BIOS_DEBUG, |
| 118 | "LPC: Opened IO window LGIR%d: base %llx size %x\n", |
| 119 | lgir_reg_num, bridge_base, window_size); |
| 120 | |
| 121 | bridged_size += window_size; |
| 122 | bridge_base += window_size; |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | void lpc_open_mmio_window(uintptr_t base, size_t size) |
| 127 | { |
| 128 | uint32_t lgmr; |
| 129 | |
| 130 | lgmr = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE); |
| 131 | |
| 132 | if (lgmr & LPC_LGMR_EN) { |
| 133 | printk(BIOS_ERR, |
| 134 | "LPC: Cannot open window to resource %lx size %zx\n", |
| 135 | base, size); |
| 136 | printk(BIOS_ERR, "LPC: MMIO window already in use\n"); |
| 137 | return; |
| 138 | } |
| 139 | |
| 140 | if (size > LPC_LGMR_WINDOW_SIZE) { |
| 141 | printk(BIOS_WARNING, |
| 142 | "LPC: Resource %lx size %zx larger than window(%x)\n", |
| 143 | base, size, LPC_LGMR_WINDOW_SIZE); |
| 144 | } |
| 145 | |
| 146 | lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; |
| 147 | |
| 148 | pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 149 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) |
| 150 | pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 153 | /* |
| 154 | * Set FAST_SPIBAR BIOS Control register based on input bit field. |
| 155 | */ |
| 156 | static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit) |
| 157 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 158 | pci_devfn_t dev = PCH_DEV_LPC; |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 159 | uint8_t bc_cntl; |
| 160 | |
Jonathan Neuschäfer | 3a182f7 | 2017-09-23 17:09:36 +0200 | [diff] [blame] | 161 | assert(IS_POWER_OF_2(bios_cntl_bit)); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 162 | bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL); |
| 163 | bc_cntl |= bios_cntl_bit; |
| 164 | pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl); |
| 165 | |
| 166 | /* |
| 167 | * Ensure an additional read back after performing lock down |
| 168 | */ |
| 169 | pci_read_config8(PCH_DEV_LPC, LPC_BIOS_CNTL); |
| 170 | } |
| 171 | |
| 172 | /* |
| 173 | * Set LPC BIOS Control BILD bit. |
| 174 | */ |
| 175 | void lpc_set_bios_interface_lock_down(void) |
| 176 | { |
| 177 | lpc_set_bios_control_reg(LPC_BC_BILD); |
| 178 | } |
| 179 | |
| 180 | /* |
| 181 | * Set LPC BIOS Control LE bit. |
| 182 | */ |
| 183 | void lpc_set_lock_enable(void) |
| 184 | { |
| 185 | lpc_set_bios_control_reg(LPC_BC_LE); |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Set LPC BIOS Control EISS bit. |
| 190 | */ |
| 191 | void lpc_set_eiss(void) |
| 192 | { |
| 193 | lpc_set_bios_control_reg(LPC_BC_EISS); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Set LPC Serial IRQ mode. |
| 198 | */ |
| 199 | void lpc_set_serirq_mode(enum serirq_mode mode) |
| 200 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 201 | pci_devfn_t dev = PCH_DEV_LPC; |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 202 | uint8_t scnt; |
| 203 | |
| 204 | scnt = pci_read_config8(dev, LPC_SERIRQ_CTL); |
| 205 | scnt &= ~(LPC_SCNT_EN | LPC_SCNT_MODE); |
| 206 | |
| 207 | switch (mode) { |
| 208 | case SERIRQ_QUIET: |
| 209 | scnt |= LPC_SCNT_EN; |
| 210 | break; |
| 211 | case SERIRQ_CONTINUOUS: |
| 212 | scnt |= LPC_SCNT_EN | LPC_SCNT_MODE; |
| 213 | break; |
| 214 | case SERIRQ_OFF: |
| 215 | default: |
| 216 | break; |
| 217 | } |
| 218 | |
| 219 | pci_write_config8(dev, LPC_SERIRQ_CTL, scnt); |
| 220 | } |
| 221 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 222 | void lpc_io_setup_comm_a_b(void) |
| 223 | { |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 224 | /* ComA Range 3F8h-3FFh [2:0] */ |
| 225 | uint16_t com_ranges = LPC_IOD_COMA_RANGE; |
| 226 | uint16_t com_enable = LPC_IOE_COMA_EN; |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 227 | uint16_t com_mask = LPC_IOD_COMA_RANGE_MASK; |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 228 | |
| 229 | /* ComB Range 2F8h-2FFh [6:4] */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 230 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 231 | com_ranges |= LPC_IOD_COMB_RANGE; |
| 232 | com_enable |= LPC_IOE_COMB_EN; |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 233 | com_mask |= LPC_IOD_COMB_RANGE_MASK; |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /* Setup I/O Decode Range Register for LPC */ |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 237 | lpc_set_fixed_io_ranges(com_ranges, com_mask); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 238 | /* Enable ComA and ComB Port */ |
Subrata Banik | d83face | 2018-03-08 14:04:52 +0530 | [diff] [blame] | 239 | lpc_enable_fixed_io_ranges(com_enable); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 240 | } |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 241 | |
| 242 | static void lpc_set_gen_decode_range( |
| 243 | uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) |
| 244 | { |
| 245 | size_t i; |
| 246 | |
| 247 | /* Set in PCI generic decode range registers */ |
Michael Niewöhner | f7e91d2 | 2021-01-17 02:51:00 +0100 | [diff] [blame] | 248 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { |
| 249 | pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); |
| 250 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) |
| 251 | pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); |
| 252 | } |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 255 | void pch_enable_lpc(void) |
| 256 | { |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 257 | uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; |
| 258 | |
Furquan Shaikh | e4f7e04 | 2020-12-23 14:11:00 -0800 | [diff] [blame] | 259 | soc_get_gen_io_dec_range(gen_io_dec); |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 260 | lpc_set_gen_decode_range(gen_io_dec); |
Subrata Banik | 42c44c2 | 2019-05-15 20:27:04 +0530 | [diff] [blame] | 261 | if (ENV_PAYLOAD_LOADER) |
Subrata Banik | 78463a7 | 2020-09-29 14:28:09 +0530 | [diff] [blame] | 262 | pch_pirq_init(); |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | void lpc_enable_pci_clk_cntl(void) |
| 266 | { |
| 267 | pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN); |
| 268 | } |
Nico Huber | dbcf293 | 2018-11-28 15:29:00 +0100 | [diff] [blame] | 269 | |
| 270 | void lpc_disable_clkrun(void) |
| 271 | { |
| 272 | const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); |
| 273 | pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); |
| 274 | } |
Subrata Banik | 1366e44 | 2020-09-29 13:55:50 +0530 | [diff] [blame] | 275 | |
| 276 | /* Enable PCH IOAPIC */ |
| 277 | void pch_enable_ioapic(void) |
| 278 | { |
| 279 | uint32_t reg32; |
| 280 | /* PCH-LP has 120 redirection entries */ |
| 281 | const int redir_entries = 120; |
| 282 | |
| 283 | set_ioapic_id((void *)IO_APIC_ADDR, 0x02); |
| 284 | |
| 285 | /* affirm full set of redirection table entries ("write once") */ |
| 286 | reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); |
| 287 | |
| 288 | reg32 &= ~0x00ff0000; |
| 289 | reg32 |= (redir_entries - 1) << 16; |
| 290 | |
| 291 | io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); |
| 292 | |
| 293 | /* |
| 294 | * Select Boot Configuration register (0x03) and |
| 295 | * use Processor System Bus (0x01) to deliver interrupts. |
| 296 | */ |
| 297 | io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); |
| 298 | } |
Subrata Banik | 78463a7 | 2020-09-29 14:28:09 +0530 | [diff] [blame] | 299 | |
| 300 | /* |
| 301 | * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 302 | * 0x00 - 0000 = Reserved |
| 303 | * 0x01 - 0001 = Reserved |
| 304 | * 0x02 - 0010 = Reserved |
| 305 | * 0x03 - 0011 = IRQ3 |
| 306 | * 0x04 - 0100 = IRQ4 |
| 307 | * 0x05 - 0101 = IRQ5 |
| 308 | * 0x06 - 0110 = IRQ6 |
| 309 | * 0x07 - 0111 = IRQ7 |
| 310 | * 0x08 - 1000 = Reserved |
| 311 | * 0x09 - 1001 = IRQ9 |
| 312 | * 0x0A - 1010 = IRQ10 |
| 313 | * 0x0B - 1011 = IRQ11 |
| 314 | * 0x0C - 1100 = IRQ12 |
| 315 | * 0x0D - 1101 = Reserved |
| 316 | * 0x0E - 1110 = IRQ14 |
| 317 | * 0x0F - 1111 = IRQ15 |
| 318 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 319 | * 0x80 - The PIRQ is not routed. |
| 320 | */ |
| 321 | void pch_pirq_init(void) |
| 322 | { |
| 323 | const struct device *irq_dev; |
| 324 | uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; |
| 325 | |
| 326 | pch_interrupt_routing[0] = PCH_IRQ11; |
| 327 | pch_interrupt_routing[1] = PCH_IRQ10; |
| 328 | pch_interrupt_routing[2] = PCH_IRQ11; |
| 329 | pch_interrupt_routing[3] = PCH_IRQ11; |
| 330 | pch_interrupt_routing[4] = PCH_IRQ11; |
| 331 | pch_interrupt_routing[5] = PCH_IRQ11; |
| 332 | pch_interrupt_routing[6] = PCH_IRQ11; |
| 333 | pch_interrupt_routing[7] = PCH_IRQ11; |
| 334 | |
| 335 | itss_irq_init(pch_interrupt_routing); |
| 336 | |
| 337 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 338 | uint8_t int_pin = 0, int_line = 0; |
| 339 | |
| 340 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 341 | continue; |
| 342 | |
| 343 | int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); |
| 344 | |
| 345 | switch (int_pin) { |
| 346 | case 1: /* INTA# */ |
| 347 | int_line = PCH_IRQ11; |
| 348 | break; |
| 349 | case 2: /* INTB# */ |
| 350 | int_line = PCH_IRQ10; |
| 351 | break; |
| 352 | case 3: /* INTC# */ |
| 353 | int_line = PCH_IRQ11; |
| 354 | break; |
| 355 | case 4: /* INTD# */ |
| 356 | int_line = PCH_IRQ11; |
| 357 | break; |
| 358 | } |
| 359 | |
| 360 | if (!int_line) |
| 361 | continue; |
| 362 | |
| 363 | pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); |
| 364 | } |
| 365 | } |
Subrata Banik | 8971ccd | 2020-09-29 14:36:40 +0530 | [diff] [blame] | 366 | |
| 367 | #define PPI_PORT_B 0x61 |
| 368 | #define SERR_DIS (1 << 2) |
| 369 | #define CMOS_NMI 0x70 |
| 370 | #define NMI_DIS (1 << 7) |
| 371 | |
| 372 | /* LPC MISC programming */ |
| 373 | void pch_misc_init(void) |
| 374 | { |
| 375 | uint8_t reg8; |
| 376 | |
| 377 | /* Setup NMI on errors, disable SERR */ |
| 378 | reg8 = (inb(PPI_PORT_B)) & 0xf0; |
| 379 | outb((reg8 | SERR_DIS), PPI_PORT_B); |
| 380 | |
| 381 | /* Disable NMI sources */ |
| 382 | outb(NMI_DIS, CMOS_NMI); |
| 383 | } |