soc/intel: Move pch_misc_init() to common code
List of changes:
1. Move pch_misc_init() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index d189a5e..67dd661 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -386,3 +386,21 @@
pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
}
}
+
+#define PPI_PORT_B 0x61
+#define SERR_DIS (1 << 2)
+#define CMOS_NMI 0x70
+#define NMI_DIS (1 << 7)
+
+/* LPC MISC programming */
+void pch_misc_init(void)
+{
+ uint8_t reg8;
+
+ /* Setup NMI on errors, disable SERR */
+ reg8 = (inb(PPI_PORT_B)) & 0xf0;
+ outb((reg8 | SERR_DIS), PPI_PORT_B);
+
+ /* Disable NMI sources */
+ outb(NMI_DIS, CMOS_NMI);
+}