soc/intel/common/block: Update LPC lib
Add support for following functionality:
1. Set up PCH LPC interrupt routing.
2. Set up generic IO decoder range settings.
3. Enable CLKRUN_EN for power gating LPC.
Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index c4144cb..0fcf383 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -235,3 +235,47 @@
/* Enable ComA and ComB Port */
lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN);
}
+
+static void lpc_set_gen_decode_range(
+ uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+{
+ size_t i;
+
+ /* Set in PCI generic decode range registers */
+ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++)
+ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
+ gen_io_dec[i]);
+}
+
+static void pch_lpc_interrupt_init(void)
+{
+ const struct device *dev;
+
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ if (!dev || !dev->chip_info)
+ return;
+
+ soc_pch_pirq_init(dev);
+}
+
+void pch_enable_lpc(void)
+{
+ /* Lookup device tree in romstage */
+ const struct device *dev;
+ uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES];
+
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ if (!dev || !dev->chip_info)
+ return;
+
+ soc_get_gen_io_dec_range(dev, gen_io_dec);
+ lpc_set_gen_decode_range(gen_io_dec);
+ soc_setup_dmi_pcr_io_dec(gen_io_dec);
+ if (ENV_RAMSTAGE)
+ pch_lpc_interrupt_init();
+}
+
+void lpc_enable_pci_clk_cntl(void)
+{
+ pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
+}