Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Patrick Rudolph | ef8c559 | 2018-07-27 17:48:27 +0200 | [diff] [blame] | 22 | #include <device/pci_def.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 23 | #include <pc80/mc146818rtc.h> |
| 24 | #include <pc80/isa-dma.h> |
| 25 | #include <pc80/i8259.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/ioapic.h> |
| 28 | #include <arch/acpi.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 29 | #include <arch/cpu.h> |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 30 | #include <arch/acpigen.h> |
| 31 | #include <drivers/intel/gma/i915.h> |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 32 | #include <cpu/x86/smm.h> |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 33 | #include <cbmem.h> |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 34 | #include <string.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 35 | #include "pch.h" |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 36 | #include "nvs.h" |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 37 | #include <southbridge/intel/common/pciehp.h> |
Tobias Diedrich | 7f5efd9 | 2017-12-14 00:29:01 +0100 | [diff] [blame] | 38 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 39 | #include <southbridge/intel/common/pmutil.h> |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 40 | #include <southbridge/intel/common/rtc.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | |
| 42 | #define NMI_OFF 0 |
| 43 | |
| 44 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 45 | |
| 46 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 47 | |
Paul Menzel | 9c50e6a | 2013-05-03 12:23:39 +0200 | [diff] [blame] | 48 | /** |
| 49 | * Set miscellanous static southbridge features. |
| 50 | * |
| 51 | * @param dev PCI device with I/O APIC control registers |
| 52 | */ |
| 53 | static void pch_enable_ioapic(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 54 | { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 55 | u32 reg32; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 56 | |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 57 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 58 | pci_write_config16(dev, LPC_IBDF, |
| 59 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 60 | |
Paul Menzel | 9c50e6a | 2013-05-03 12:23:39 +0200 | [diff] [blame] | 61 | /* Enable ACPI I/O range decode */ |
| 62 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 63 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 64 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 65 | |
| 66 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 67 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
| 68 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 69 | |
Paul Menzel | 9c50e6a | 2013-05-03 12:23:39 +0200 | [diff] [blame] | 70 | /* |
| 71 | * Select Boot Configuration register (0x03) and |
| 72 | * use Processor System Bus (0x01) to deliver interrupts. |
| 73 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 74 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static void pch_enable_serial_irqs(struct device *dev) |
| 78 | { |
| 79 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 80 | pci_write_config8(dev, SERIRQ_CNTL, |
| 81 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 82 | #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 83 | pci_write_config8(dev, SERIRQ_CNTL, |
| 84 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 85 | #endif |
| 86 | } |
| 87 | |
| 88 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 89 | * 0x00 - 0000 = Reserved |
| 90 | * 0x01 - 0001 = Reserved |
| 91 | * 0x02 - 0010 = Reserved |
| 92 | * 0x03 - 0011 = IRQ3 |
| 93 | * 0x04 - 0100 = IRQ4 |
| 94 | * 0x05 - 0101 = IRQ5 |
| 95 | * 0x06 - 0110 = IRQ6 |
| 96 | * 0x07 - 0111 = IRQ7 |
| 97 | * 0x08 - 1000 = Reserved |
| 98 | * 0x09 - 1001 = IRQ9 |
| 99 | * 0x0A - 1010 = IRQ10 |
| 100 | * 0x0B - 1011 = IRQ11 |
| 101 | * 0x0C - 1100 = IRQ12 |
| 102 | * 0x0D - 1101 = Reserved |
| 103 | * 0x0E - 1110 = IRQ14 |
| 104 | * 0x0F - 1111 = IRQ15 |
| 105 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 106 | * 0x80 - The PIRQ is not routed. |
| 107 | */ |
| 108 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 109 | static void pch_pirq_init(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 110 | { |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 111 | struct device *irq_dev; |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 112 | /* Interrupt 11 is not used by legacy devices and so can always be used for |
| 113 | PCI interrupts. Full legacy IRQ routing is complicated and hard to |
| 114 | get right. Fortunately all modern OS use MSI and so it's not that big of |
| 115 | an issue anyway. Still we have to provide a reasonable default. Using |
| 116 | interrupt 11 for it everywhere is a working default. ACPI-aware OS can |
| 117 | move it to any interrupt and others will just leave them at default. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 118 | */ |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 119 | const u8 pirq_routing = 11; |
| 120 | |
| 121 | pci_write_config8(dev, PIRQA_ROUT, pirq_routing); |
| 122 | pci_write_config8(dev, PIRQB_ROUT, pirq_routing); |
| 123 | pci_write_config8(dev, PIRQC_ROUT, pirq_routing); |
| 124 | pci_write_config8(dev, PIRQD_ROUT, pirq_routing); |
| 125 | |
| 126 | pci_write_config8(dev, PIRQE_ROUT, pirq_routing); |
| 127 | pci_write_config8(dev, PIRQF_ROUT, pirq_routing); |
| 128 | pci_write_config8(dev, PIRQG_ROUT, pirq_routing); |
| 129 | pci_write_config8(dev, PIRQH_ROUT, pirq_routing); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 130 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 131 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 132 | u8 int_pin=0; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 133 | |
| 134 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 135 | continue; |
| 136 | |
| 137 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 138 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 139 | if (int_pin == 0) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 140 | continue; |
| 141 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 142 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 143 | } |
| 144 | } |
| 145 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 146 | static void pch_gpi_routing(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 147 | { |
| 148 | /* Get the chip configuration */ |
| 149 | config_t *config = dev->chip_info; |
| 150 | u32 reg32 = 0; |
| 151 | |
| 152 | /* An array would be much nicer here, or some |
| 153 | * other method of doing this. |
| 154 | */ |
| 155 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 156 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 157 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 158 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 159 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 160 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 161 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 162 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 163 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 164 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 165 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 166 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 167 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 168 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 169 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 170 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 171 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 172 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 173 | } |
| 174 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 175 | static void pch_power_options(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 176 | { |
| 177 | u8 reg8; |
| 178 | u16 reg16, pmbase; |
| 179 | u32 reg32; |
| 180 | const char *state; |
| 181 | /* Get the chip configuration */ |
| 182 | config_t *config = dev->chip_info; |
| 183 | |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 184 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 185 | int nmi_option; |
| 186 | |
| 187 | /* Which state do we want to goto after g3 (power restored)? |
| 188 | * 0 == S0 Full On |
| 189 | * 1 == S5 Soft Off |
| 190 | * |
| 191 | * If the option is not existent (Laptops), use Kconfig setting. |
| 192 | */ |
| 193 | get_option(&pwr_on, "power_on_after_fail"); |
| 194 | |
| 195 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 196 | reg16 &= 0xfffe; |
| 197 | switch (pwr_on) { |
| 198 | case MAINBOARD_POWER_OFF: |
| 199 | reg16 |= 1; |
| 200 | state = "off"; |
| 201 | break; |
| 202 | case MAINBOARD_POWER_ON: |
| 203 | reg16 &= ~1; |
| 204 | state = "on"; |
| 205 | break; |
| 206 | case MAINBOARD_POWER_KEEP: |
| 207 | reg16 &= ~1; |
| 208 | state = "state keep"; |
| 209 | break; |
| 210 | default: |
| 211 | state = "undefined"; |
| 212 | } |
| 213 | |
| 214 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 215 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 216 | |
| 217 | reg16 &= ~(1 << 10); |
| 218 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 219 | |
| 220 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 221 | |
| 222 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 223 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 224 | |
| 225 | /* Set up NMI on errors. */ |
| 226 | reg8 = inb(0x61); |
| 227 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 228 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 229 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 230 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 231 | outb(reg8, 0x61); |
| 232 | |
| 233 | reg8 = inb(0x70); |
| 234 | nmi_option = NMI_OFF; |
| 235 | get_option(&nmi_option, "nmi"); |
| 236 | if (nmi_option) { |
| 237 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 238 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 239 | } else { |
| 240 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 241 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 242 | } |
| 243 | outb(reg8, 0x70); |
| 244 | |
| 245 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 246 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 247 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 248 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
| 249 | #if DEBUG_PERIODIC_SMIS |
| 250 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 251 | * periodic SMIs. |
| 252 | */ |
| 253 | reg16 |= (3 << 0); // Periodic SMI every 8s |
| 254 | #endif |
| 255 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 256 | |
| 257 | // Set the board's GPI routing. |
| 258 | pch_gpi_routing(dev); |
| 259 | |
| 260 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 261 | |
| 262 | outl(config->gpe0_en, pmbase + GPE0_EN); |
| 263 | outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); |
| 264 | |
| 265 | /* Set up power management block and determine sleep mode */ |
| 266 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 267 | reg32 &= ~(7 << 10); // SLP_TYP |
| 268 | reg32 |= (1 << 0); // SCI_EN |
| 269 | outl(reg32, pmbase + 0x04); |
| 270 | |
| 271 | /* Clear magic status bits to prevent unexpected wake */ |
| 272 | reg32 = RCBA32(0x3310); |
| 273 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 274 | RCBA32(0x3310) = reg32; |
| 275 | |
| 276 | reg32 = RCBA32(0x3f02); |
| 277 | reg32 &= ~0xf; |
| 278 | RCBA32(0x3f02) = reg32; |
| 279 | } |
| 280 | |
Duncan Laurie | 3f6a4d7 | 2012-06-28 13:03:40 -0700 | [diff] [blame] | 281 | /* CougarPoint PCH Power Management init */ |
| 282 | static void cpt_pm_init(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 283 | { |
Duncan Laurie | 3f6a4d7 | 2012-06-28 13:03:40 -0700 | [diff] [blame] | 284 | printk(BIOS_DEBUG, "CougarPoint PM init\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 285 | pci_write_config8(dev, 0xa9, 0x47); |
| 286 | RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); |
| 287 | RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); |
| 288 | RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); |
| 289 | RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); |
| 290 | RCBA32(0x2304) = 0xc0388400; |
| 291 | RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); |
| 292 | RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); |
| 293 | RCBA32_AND_OR(0x3314, ~0x1f, 0xf); |
| 294 | RCBA32(0x3318) = 0x050f0000; |
| 295 | RCBA32(0x3324) = 0x04000000; |
| 296 | RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); |
| 297 | RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); |
| 298 | RCBA32(0x3360) = 0x0001c000; |
| 299 | RCBA32(0x3368) = 0x00061100; |
| 300 | RCBA32(0x3378) = 0x7f8fdfff; |
| 301 | RCBA32(0x337c) = 0x000003fc; |
| 302 | RCBA32(0x3388) = 0x00001000; |
| 303 | RCBA32(0x3390) = 0x0001c000; |
| 304 | RCBA32(0x33a0) = 0x00000800; |
| 305 | RCBA32(0x33b0) = 0x00001000; |
| 306 | RCBA32(0x33c0) = 0x00093900; |
| 307 | RCBA32(0x33cc) = 0x24653002; |
| 308 | RCBA32(0x33d0) = 0x062108fe; |
| 309 | RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); |
| 310 | RCBA32(0x3a28) = 0x01010000; |
| 311 | RCBA32(0x3a2c) = 0x01010404; |
| 312 | RCBA32(0x3a80) = 0x01041041; |
| 313 | RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); |
| 314 | RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ |
| 315 | RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ |
| 316 | RCBA32(0x3a6c) = 0x00000001; |
| 317 | RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); |
| 318 | RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); |
| 319 | RCBA32(0x33c8) = 0; |
| 320 | RCBA32_AND_OR(0x21b0, ~0UL, 0xf); |
| 321 | } |
| 322 | |
Duncan Laurie | 3f6a4d7 | 2012-06-28 13:03:40 -0700 | [diff] [blame] | 323 | /* PantherPoint PCH Power Management init */ |
| 324 | static void ppt_pm_init(struct device *dev) |
| 325 | { |
| 326 | printk(BIOS_DEBUG, "PantherPoint PM init\n"); |
| 327 | pci_write_config8(dev, 0xa9, 0x47); |
| 328 | RCBA32_AND_OR(0x2238, ~0UL, (1 << 0)); |
| 329 | RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); |
| 330 | RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); |
| 331 | RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); |
| 332 | RCBA32(0x2304) = 0xc03b8400; |
| 333 | RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); |
| 334 | RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); |
| 335 | RCBA32_AND_OR(0x3314, ~0x1f, 0xf); |
| 336 | RCBA32(0x3318) = 0x054f0000; |
| 337 | RCBA32(0x3324) = 0x04000000; |
| 338 | RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); |
| 339 | RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0)); |
| 340 | RCBA32(0x3360) = 0x0001c000; |
| 341 | RCBA32(0x3368) = 0x00061100; |
| 342 | RCBA32(0x3378) = 0x7f8fdfff; |
| 343 | RCBA32(0x337c) = 0x000003fd; |
| 344 | RCBA32(0x3388) = 0x00001000; |
| 345 | RCBA32(0x3390) = 0x0001c000; |
| 346 | RCBA32(0x33a0) = 0x00000800; |
| 347 | RCBA32(0x33b0) = 0x00001000; |
| 348 | RCBA32(0x33c0) = 0x00093900; |
| 349 | RCBA32(0x33cc) = 0x24653002; |
| 350 | RCBA32(0x33d0) = 0x067388fe; |
| 351 | RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); |
| 352 | RCBA32(0x3a28) = 0x01010000; |
| 353 | RCBA32(0x3a2c) = 0x01010404; |
| 354 | RCBA32(0x3a80) = 0x01040000; |
| 355 | RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); |
| 356 | RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ |
| 357 | RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ |
| 358 | RCBA32(0x3a6c) = 0x00000001; |
| 359 | RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); |
| 360 | RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); |
| 361 | RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0)); |
| 362 | RCBA32(0x33c8) = 0; |
| 363 | RCBA32_AND_OR(0x21b0, ~0UL, 0xf); |
| 364 | } |
| 365 | |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 366 | static void enable_hpet(struct device *const dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 367 | { |
| 368 | u32 reg32; |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 369 | size_t i; |
| 370 | |
| 371 | /* Assign unique bus/dev/fn for each HPET */ |
| 372 | for (i = 0; i < 8; ++i) |
| 373 | pci_write_config16(dev, LPC_HnBDF(i), |
| 374 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 375 | |
| 376 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 377 | reg32 = RCBA32(HPTC); |
| 378 | reg32 |= (1 << 7); // HPET Address Enable |
| 379 | reg32 &= ~(3 << 0); |
| 380 | RCBA32(HPTC) = reg32; |
| 381 | } |
| 382 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 383 | static void enable_clock_gating(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 384 | { |
| 385 | u32 reg32; |
| 386 | u16 reg16; |
| 387 | |
| 388 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 389 | |
| 390 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 391 | reg16 |= (1 << 2) | (1 << 11); |
| 392 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 393 | |
| 394 | pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); |
| 395 | pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); |
| 396 | pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); |
| 397 | pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); |
| 398 | |
| 399 | reg32 = RCBA32(CG); |
| 400 | reg32 |= (1 << 31); |
| 401 | reg32 |= (1 << 29) | (1 << 28); |
| 402 | reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); |
| 403 | reg32 |= (1 << 16); |
| 404 | reg32 |= (1 << 17); |
| 405 | reg32 |= (1 << 18); |
| 406 | reg32 |= (1 << 22); |
| 407 | reg32 |= (1 << 23); |
| 408 | reg32 &= ~(1 << 20); |
| 409 | reg32 |= (1 << 19); |
| 410 | reg32 |= (1 << 0); |
| 411 | reg32 |= (0xf << 1); |
| 412 | RCBA32(CG) = reg32; |
| 413 | |
| 414 | RCBA32_OR(0x38c0, 0x7); |
| 415 | RCBA32_OR(0x36d4, 0x6680c004); |
| 416 | RCBA32_OR(0x3564, 0x3); |
| 417 | } |
| 418 | |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 419 | static void pch_set_acpi_mode(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 420 | { |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 421 | if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 422 | #if ENABLE_ACPI_MODE_IN_COREBOOT |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 423 | printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 424 | outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 425 | printk(BIOS_DEBUG, "done.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 426 | #else |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 427 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 428 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 429 | printk(BIOS_DEBUG, "done.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 430 | #endif |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 431 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 432 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 433 | |
| 434 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 435 | { |
| 436 | u8 reg8; |
| 437 | |
| 438 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
| 439 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 440 | reg8 &= ~(1 << 5); |
| 441 | pci_write_config8(dev, 0xdc, reg8); |
| 442 | } |
| 443 | |
| 444 | static void pch_fixups(struct device *dev) |
| 445 | { |
| 446 | u8 gen_pmcon_2; |
| 447 | |
| 448 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 449 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 450 | gen_pmcon_2 |= (1 << 7); |
| 451 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 452 | |
| 453 | /* |
| 454 | * Enable DMI ASPM in the PCH |
| 455 | */ |
| 456 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 457 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 458 | RCBA32_OR(0x21a8, 0x3); |
| 459 | } |
| 460 | |
| 461 | static void pch_decode_init(struct device *dev) |
| 462 | { |
| 463 | config_t *config = dev->chip_info; |
| 464 | |
| 465 | printk(BIOS_DEBUG, "pch_decode_init\n"); |
| 466 | |
| 467 | pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); |
| 468 | pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); |
| 469 | pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); |
| 470 | pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); |
| 471 | } |
| 472 | |
Nico Huber | 7b2f9f6 | 2015-10-01 19:00:51 +0200 | [diff] [blame] | 473 | static void pch_spi_init(const struct device *const dev) |
| 474 | { |
| 475 | const config_t *const config = dev->chip_info; |
| 476 | |
| 477 | printk(BIOS_DEBUG, "pch_spi_init\n"); |
| 478 | |
| 479 | if (config->spi_uvscc) |
| 480 | RCBA32(0x3800 + 0xc8) = config->spi_uvscc; |
| 481 | if (config->spi_lvscc) |
| 482 | RCBA32(0x3800 + 0xc4) = config->spi_lvscc; |
| 483 | |
| 484 | if (config->spi_uvscc || config->spi_lvscc) |
| 485 | RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */ |
| 486 | } |
| 487 | |
Patrick Rudolph | ef8c559 | 2018-07-27 17:48:27 +0200 | [diff] [blame] | 488 | static const struct { |
| 489 | u16 dev_id; |
| 490 | const char *dev_name; |
| 491 | } pch_table[] = { |
| 492 | /* 6-series PCI ids from |
| 493 | * Intel® 6 Series Chipset and |
| 494 | * Intel® C200 Series Chipset |
| 495 | * Specification Update - NDA |
| 496 | * October 2013 |
| 497 | * CDI / IBP#: 440377 |
| 498 | */ |
| 499 | {0x1C41, "SFF Sample"}, |
| 500 | {0x1C42, "Desktop Sample"}, |
| 501 | {0x1C43, "Mobile Sample"}, |
| 502 | {0x1C44, "Z68"}, |
| 503 | {0x1C46, "P67"}, |
| 504 | {0x1C47, "UM67"}, |
| 505 | {0x1C49, "HM65"}, |
| 506 | {0x1C4A, "H67"}, |
| 507 | {0x1C4B, "HM67"}, |
| 508 | {0x1C4C, "Q65"}, |
| 509 | {0x1C4D, "QS67"}, |
| 510 | {0x1C4E, "Q67"}, |
| 511 | {0x1C4F, "QM67"}, |
| 512 | {0x1C50, "B65"}, |
| 513 | {0x1C52, "C202"}, |
| 514 | {0x1C54, "C204"}, |
| 515 | {0x1C56, "C206"}, |
| 516 | {0x1C5C, "H61"}, |
| 517 | /* 7-series PCI ids from Intel document 472178 */ |
| 518 | {0x1E41, "Desktop Sample"}, |
| 519 | {0x1E42, "Mobile Sample"}, |
| 520 | {0x1E43, "SFF Sample"}, |
| 521 | {0x1E44, "Z77"}, |
| 522 | {0x1E45, "H71"}, |
| 523 | {0x1E46, "Z75"}, |
| 524 | {0x1E47, "Q77"}, |
| 525 | {0x1E48, "Q75"}, |
| 526 | {0x1E49, "B75"}, |
| 527 | {0x1E4A, "H77"}, |
| 528 | {0x1E53, "C216"}, |
| 529 | {0x1E55, "QM77"}, |
| 530 | {0x1E56, "QS77"}, |
| 531 | {0x1E58, "UM77"}, |
| 532 | {0x1E57, "HM77"}, |
| 533 | {0x1E59, "HM76"}, |
| 534 | {0x1E5D, "HM75"}, |
| 535 | {0x1E5E, "HM70"}, |
| 536 | {0x1E5F, "NM70"}, |
| 537 | }; |
| 538 | |
| 539 | static void report_pch_info(struct device *dev) |
| 540 | { |
| 541 | const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID); |
| 542 | int i; |
| 543 | |
| 544 | const char *pch_type = "Unknown"; |
| 545 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 546 | if (pch_table[i].dev_id == dev_id) { |
| 547 | pch_type = pch_table[i].dev_name; |
| 548 | break; |
| 549 | } |
| 550 | } |
| 551 | printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n", |
| 552 | pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION)); |
| 553 | } |
| 554 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 555 | static void lpc_init(struct device *dev) |
| 556 | { |
| 557 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 558 | |
Patrick Rudolph | ef8c559 | 2018-07-27 17:48:27 +0200 | [diff] [blame] | 559 | /* Print detected platform */ |
| 560 | report_pch_info(dev); |
| 561 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 562 | /* Set the value for PCI command register. */ |
| 563 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 564 | |
| 565 | /* IO APIC initialization. */ |
Paul Menzel | 9c50e6a | 2013-05-03 12:23:39 +0200 | [diff] [blame] | 566 | pch_enable_ioapic(dev); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 567 | |
| 568 | pch_enable_serial_irqs(dev); |
| 569 | |
| 570 | /* Setup the PIRQ. */ |
| 571 | pch_pirq_init(dev); |
| 572 | |
| 573 | /* Setup power options. */ |
| 574 | pch_power_options(dev); |
| 575 | |
| 576 | /* Initialize power management */ |
Duncan Laurie | 3f6a4d7 | 2012-06-28 13:03:40 -0700 | [diff] [blame] | 577 | switch (pch_silicon_type()) { |
| 578 | case PCH_TYPE_CPT: /* CougarPoint */ |
| 579 | cpt_pm_init(dev); |
| 580 | break; |
| 581 | case PCH_TYPE_PPT: /* PantherPoint */ |
| 582 | ppt_pm_init(dev); |
| 583 | break; |
| 584 | default: |
| 585 | printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); |
| 586 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 587 | |
| 588 | /* Set the state of the GPIO lines. */ |
| 589 | //gpio_init(dev); |
| 590 | |
| 591 | /* Initialize the real time clock. */ |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 592 | sb_rtc_init(); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 593 | |
| 594 | /* Initialize ISA DMA. */ |
| 595 | isa_dma_init(); |
| 596 | |
| 597 | /* Initialize the High Precision Event Timers, if present. */ |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 598 | enable_hpet(dev); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 599 | |
| 600 | /* Initialize Clock Gating */ |
| 601 | enable_clock_gating(dev); |
| 602 | |
| 603 | setup_i8259(); |
| 604 | |
| 605 | /* The OS should do this? */ |
| 606 | /* Interrupt 9 should be level triggered (SCI) */ |
| 607 | i8259_configure_irq_trigger(9, 1); |
| 608 | |
| 609 | pch_disable_smm_only_flashing(dev); |
| 610 | |
Vladimir Serbinenko | a3e41c0 | 2015-05-28 16:04:17 +0200 | [diff] [blame] | 611 | pch_set_acpi_mode(); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 612 | |
| 613 | pch_fixups(dev); |
Nico Huber | 7b2f9f6 | 2015-10-01 19:00:51 +0200 | [diff] [blame] | 614 | |
| 615 | pch_spi_init(dev); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 616 | } |
| 617 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 618 | static void pch_lpc_read_resources(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 619 | { |
| 620 | struct resource *res; |
Marc Jones | a0bec17 | 2012-07-13 14:14:34 -0600 | [diff] [blame] | 621 | config_t *config = dev->chip_info; |
| 622 | u8 io_index = 0; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 623 | |
| 624 | /* Get the normal PCI resources of this device. */ |
| 625 | pci_dev_read_resources(dev); |
| 626 | |
| 627 | /* Add an extra subtractive resource for both memory and I/O. */ |
Marc Jones | a0bec17 | 2012-07-13 14:14:34 -0600 | [diff] [blame] | 628 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 629 | res->base = 0; |
| 630 | res->size = 0x1000; |
| 631 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 632 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 633 | |
Marc Jones | a0bec17 | 2012-07-13 14:14:34 -0600 | [diff] [blame] | 634 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
Vladimir Serbinenko | 0650cd0 | 2014-02-05 15:03:50 +0100 | [diff] [blame] | 635 | res->base = 0xff000000; |
| 636 | /* Some systems (e.g. X230) have 12 MiB flash. |
| 637 | SPI controller supports up to 2 x 16 MiB of flash but |
| 638 | address map limits this to 16MiB. */ |
| 639 | res->size = 0x01000000; /* 16 MB for flash */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 640 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 641 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 642 | |
| 643 | res = new_resource(dev, 3); /* IOAPIC */ |
| 644 | res->base = IO_APIC_ADDR; |
| 645 | res->size = 0x00001000; |
| 646 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Marc Jones | a0bec17 | 2012-07-13 14:14:34 -0600 | [diff] [blame] | 647 | |
| 648 | /* Set PCH IO decode ranges if required.*/ |
| 649 | if ((config->gen1_dec & 0xFFFC) > 0x1000) { |
| 650 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 651 | res->base = config->gen1_dec & 0xFFFC; |
| 652 | res->size = (config->gen1_dec >> 16) & 0xFC; |
| 653 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 654 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 655 | } |
| 656 | |
| 657 | if ((config->gen2_dec & 0xFFFC) > 0x1000) { |
| 658 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 659 | res->base = config->gen2_dec & 0xFFFC; |
| 660 | res->size = (config->gen2_dec >> 16) & 0xFC; |
| 661 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 662 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 663 | } |
| 664 | |
| 665 | if ((config->gen3_dec & 0xFFFC) > 0x1000) { |
| 666 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 667 | res->base = config->gen3_dec & 0xFFFC; |
| 668 | res->size = (config->gen3_dec >> 16) & 0xFC; |
| 669 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 670 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 671 | } |
| 672 | |
| 673 | if ((config->gen4_dec & 0xFFFC) > 0x1000) { |
| 674 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 675 | res->base = config->gen4_dec & 0xFFFC; |
| 676 | res->size = (config->gen4_dec >> 16) & 0xFC; |
| 677 | res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | |
| 678 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 679 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 680 | } |
| 681 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 682 | static void pch_lpc_enable_resources(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 683 | { |
| 684 | pch_decode_init(dev); |
| 685 | return pci_dev_enable_resources(dev); |
| 686 | } |
| 687 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 688 | static void pch_lpc_enable(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 689 | { |
| 690 | /* Enable PCH Display Port */ |
| 691 | RCBA16(DISPBDF) = 0x0010; |
| 692 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 693 | |
| 694 | pch_enable(dev); |
| 695 | } |
| 696 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 697 | static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 698 | { |
| 699 | if (!vendor || !device) { |
| 700 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 701 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 702 | } else { |
| 703 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 704 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 705 | } |
| 706 | } |
| 707 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 708 | static void southbridge_inject_dsdt(struct device *dev) |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 709 | { |
Elyes HAOUAS | 035df00 | 2016-10-03 21:54:16 +0200 | [diff] [blame] | 710 | global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 711 | |
| 712 | if (gnvs) { |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 713 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Elyes HAOUAS | 035df00 | 2016-10-03 21:54:16 +0200 | [diff] [blame] | 714 | memset(gnvs, 0, sizeof(*gnvs)); |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 715 | |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 716 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | 06c788d | 2014-10-12 00:17:11 +0200 | [diff] [blame] | 717 | |
| 718 | gnvs->apic = 1; |
| 719 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 720 | gnvs->pcnt = dev_count_cpu(); |
| 721 | |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 722 | if (gfx) { |
| 723 | gnvs->ndid = gfx->ndid; |
| 724 | memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); |
| 725 | } |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 726 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 727 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 728 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
Vladimir Serbinenko | 06c788d | 2014-10-12 00:17:11 +0200 | [diff] [blame] | 729 | #endif |
| 730 | |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 731 | /* And tell SMI about it */ |
| 732 | smm_setup_structures(gnvs, NULL, NULL); |
| 733 | |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 734 | /* Add it to DSDT. */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 735 | acpigen_write_scope("\\"); |
| 736 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 737 | acpigen_pop_len(); |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 738 | } |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 739 | } |
| 740 | |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 741 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 742 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 743 | struct device *dev = pcidev_on_root(0x1f, 0); |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 744 | config_t *chip = dev->chip_info; |
| 745 | u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 746 | int c2_latency; |
| 747 | |
Elyes HAOUAS | 0d4de2a | 2019-02-28 13:04:29 +0100 | [diff] [blame^] | 748 | fadt->reserved = 0; |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 749 | |
| 750 | fadt->sci_int = 0x9; |
| 751 | fadt->smi_cmd = APM_CNT; |
| 752 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 753 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 754 | fadt->s4bios_req = 0x0; |
| 755 | fadt->pstate_cnt = 0; |
| 756 | |
| 757 | fadt->pm1a_evt_blk = pmbase; |
| 758 | fadt->pm1b_evt_blk = 0x0; |
| 759 | fadt->pm1a_cnt_blk = pmbase + 0x4; |
| 760 | fadt->pm1b_cnt_blk = 0x0; |
| 761 | fadt->pm2_cnt_blk = pmbase + 0x50; |
| 762 | fadt->pm_tmr_blk = pmbase + 0x8; |
| 763 | fadt->gpe0_blk = pmbase + 0x20; |
| 764 | fadt->gpe1_blk = 0; |
| 765 | |
| 766 | fadt->pm1_evt_len = 4; |
| 767 | fadt->pm1_cnt_len = 2; |
| 768 | fadt->pm2_cnt_len = 1; |
| 769 | fadt->pm_tmr_len = 4; |
| 770 | fadt->gpe0_blk_len = 16; |
| 771 | fadt->gpe1_blk_len = 0; |
| 772 | fadt->gpe1_base = 0; |
| 773 | fadt->cst_cnt = 0; |
| 774 | c2_latency = chip->c2_latency; |
| 775 | if (!c2_latency) { |
| 776 | c2_latency = 101; /* c2 unsupported */ |
| 777 | } |
| 778 | fadt->p_lvl2_lat = c2_latency; |
| 779 | fadt->p_lvl3_lat = 87; |
| 780 | fadt->flush_size = 1024; |
| 781 | fadt->flush_stride = 16; |
| 782 | fadt->duty_offset = 1; |
| 783 | if (chip->p_cnt_throttling_supported) { |
| 784 | fadt->duty_width = 3; |
| 785 | } else { |
| 786 | fadt->duty_width = 0; |
| 787 | } |
| 788 | fadt->day_alrm = 0xd; |
| 789 | fadt->mon_alrm = 0x00; |
| 790 | fadt->century = 0x00; |
| 791 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 792 | |
| 793 | fadt->flags = ACPI_FADT_WBINVD | |
| 794 | ACPI_FADT_C1_SUPPORTED | |
| 795 | ACPI_FADT_SLEEP_BUTTON | |
| 796 | ACPI_FADT_RESET_REGISTER | |
| 797 | ACPI_FADT_SEALED_CASE | |
| 798 | ACPI_FADT_S4_RTC_WAKE | |
| 799 | ACPI_FADT_PLATFORM_CLOCK; |
| 800 | if (chip->docking_supported) { |
| 801 | fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; |
| 802 | } |
| 803 | if (c2_latency < 100) { |
| 804 | fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; |
| 805 | } |
| 806 | |
| 807 | fadt->reset_reg.space_id = 1; |
| 808 | fadt->reset_reg.bit_width = 8; |
| 809 | fadt->reset_reg.bit_offset = 0; |
| 810 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 811 | fadt->reset_reg.addrl = 0xcf9; |
| 812 | fadt->reset_reg.addrh = 0; |
| 813 | |
| 814 | fadt->reset_value = 6; |
| 815 | |
| 816 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 817 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 818 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 819 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 820 | fadt->x_pm1a_evt_blk.addrl = pmbase; |
| 821 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 822 | |
| 823 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 824 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 825 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 826 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 827 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 828 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 829 | |
| 830 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 831 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 832 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 833 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 834 | fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; |
| 835 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 836 | |
| 837 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 838 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 839 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 840 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 841 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 842 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 843 | |
| 844 | fadt->x_pm2_cnt_blk.space_id = 1; |
| 845 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 846 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 847 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 848 | fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; |
| 849 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 850 | |
| 851 | fadt->x_pm_tmr_blk.space_id = 1; |
| 852 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 853 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 854 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 855 | fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; |
| 856 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 857 | |
| 858 | fadt->x_gpe0_blk.space_id = 1; |
| 859 | fadt->x_gpe0_blk.bit_width = 128; |
| 860 | fadt->x_gpe0_blk.bit_offset = 0; |
| 861 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 862 | fadt->x_gpe0_blk.addrl = pmbase + 0x20; |
| 863 | fadt->x_gpe0_blk.addrh = 0x0; |
| 864 | |
| 865 | fadt->x_gpe1_blk.space_id = 1; |
| 866 | fadt->x_gpe1_blk.bit_width = 0; |
| 867 | fadt->x_gpe1_blk.bit_offset = 0; |
| 868 | fadt->x_gpe1_blk.access_size = 0; |
| 869 | fadt->x_gpe1_blk.addrl = 0x0; |
| 870 | fadt->x_gpe1_blk.addrh = 0x0; |
| 871 | } |
| 872 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 873 | static const char *lpc_acpi_name(const struct device *dev) |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 874 | { |
| 875 | return "LPCB"; |
| 876 | } |
| 877 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 878 | static void southbridge_fill_ssdt(struct device *device) |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 879 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 880 | struct device *dev = pcidev_on_root(0x1f, 0); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 881 | config_t *chip = dev->chip_info; |
| 882 | |
| 883 | intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); |
Tobias Diedrich | 7f5efd9 | 2017-12-14 00:29:01 +0100 | [diff] [blame] | 884 | intel_acpi_gen_def_acpi_pirq(dev); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 885 | } |
| 886 | |
Vladimir Serbinenko | b06a249 | 2015-05-21 10:32:59 +0200 | [diff] [blame] | 887 | static void lpc_final(struct device *dev) |
| 888 | { |
Nico Huber | 8e50b6d | 2018-02-04 15:52:18 +0100 | [diff] [blame] | 889 | u16 spi_opprefix = SPI_OPPREFIX; |
| 890 | u16 spi_optype = SPI_OPTYPE; |
| 891 | u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }; |
| 892 | |
| 893 | /* Configure SPI opcode menu; devicetree may override defaults. */ |
| 894 | const config_t *const config = dev->chip_info; |
| 895 | if (config && config->spi.ops[0].op) { |
| 896 | unsigned int i; |
| 897 | |
| 898 | spi_opprefix = 0; |
| 899 | spi_optype = 0; |
| 900 | spi_opmenu[0] = 0; |
| 901 | spi_opmenu[1] = 0; |
| 902 | for (i = 0; i < sizeof(spi_opprefix); ++i) |
| 903 | spi_opprefix |= config->spi.opprefixes[i] << i * 8; |
| 904 | for (i = 0; i < sizeof(spi_opmenu); ++i) { |
| 905 | spi_optype |= |
| 906 | config->spi.ops[i].is_write << 2 * i | |
| 907 | config->spi.ops[i].needs_address << (2 * i + 1); |
| 908 | spi_opmenu[i / 4] |= |
| 909 | config->spi.ops[i].op << (i % 4) * 8; |
| 910 | } |
| 911 | } |
| 912 | RCBA16(0x3894) = spi_opprefix; |
| 913 | RCBA16(0x3896) = spi_optype; |
| 914 | RCBA32(0x3898) = spi_opmenu[0]; |
| 915 | RCBA32(0x389c) = spi_opmenu[1]; |
| 916 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 917 | /* Call SMM finalize() handlers before resume */ |
| 918 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
| 919 | if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || |
| 920 | acpi_is_wakeup_s3()) { |
| 921 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 922 | } |
Vladimir Serbinenko | b06a249 | 2015-05-21 10:32:59 +0200 | [diff] [blame] | 923 | } |
| 924 | } |
| 925 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 926 | static struct pci_operations pci_ops = { |
| 927 | .set_subsystem = set_subsystem, |
| 928 | }; |
| 929 | |
| 930 | static struct device_operations device_ops = { |
| 931 | .read_resources = pch_lpc_read_resources, |
| 932 | .set_resources = pci_dev_set_resources, |
| 933 | .enable_resources = pch_lpc_enable_resources, |
Vladimir Serbinenko | 35c0f43 | 2014-09-02 22:25:36 +0200 | [diff] [blame] | 934 | .write_acpi_tables = acpi_write_hpet, |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 935 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 936 | .acpi_fill_ssdt_generator = southbridge_fill_ssdt, |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 937 | .acpi_name = lpc_acpi_name, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 938 | .init = lpc_init, |
Vladimir Serbinenko | b06a249 | 2015-05-21 10:32:59 +0200 | [diff] [blame] | 939 | .final = lpc_final, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 940 | .enable = pch_lpc_enable, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 941 | .scan_bus = scan_lpc_bus, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 942 | .ops_pci = &pci_ops, |
| 943 | }; |
| 944 | |
| 945 | |
Kimarie Hoot | e6f459c | 2012-07-14 08:26:08 -0600 | [diff] [blame] | 946 | /* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and |
| 947 | * Intel C200 Series Chipset |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 948 | */ |
| 949 | |
Vladimir Serbinenko | 42d55e0 | 2016-01-02 01:47:26 +0100 | [diff] [blame] | 950 | static const unsigned short pci_device_ids[] = { |
| 951 | 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, |
| 952 | 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, |
| 953 | 0x1c52, 0x1c53, 0x1c54, 0x1c55, 0x1c56, 0x1c57, 0x1c58, 0x1c59, 0x1c5a, |
| 954 | 0x1c5b, 0x1c5c, 0x1c5d, 0x1c5e, 0x1c5f, |
| 955 | |
| 956 | 0x1e41, 0x1e42, 0x1e43, 0x1e44, 0x1e45, 0x1e46, 0x1e47, 0x1e48, 0x1e49, |
| 957 | 0x1e4a, 0x1e4b, 0x1e4c, 0x1e4d, 0x1e4e, 0x1e4f, 0x1e50, 0x1e51, 0x1e52, |
| 958 | 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, |
| 959 | 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f, |
| 960 | |
| 961 | 0 }; |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 962 | |
| 963 | static const struct pci_driver pch_lpc __pci_driver = { |
| 964 | .ops = &device_ops, |
| 965 | .vendor = PCI_VENDOR_ID_INTEL, |
| 966 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 967 | }; |