commit 36fa5b80843d836518eb89f46747e80ed6b5d96f
author Vladimir Serbinenko <phcoder@gmail.com> Tue Oct 28 23:43:20 2014 +0100
committer Vladimir Serbinenko <phcoder@gmail.com> Wed Nov 19 21:09:51 2014 +0100
tree a36f498a48aaa8764df768ff3616ff476f62a07b
parent 10dd0e3171bc631fd5d83d4f42aa376edd3c6d55

i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug

This implementation is more compact, unified and works with windows as well.

Tested under windows and under Debian GNU/Linux.

Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7296
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)

src/southbridge/intel/bd82x6x/lpc.c

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 80d6284..3c55946 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -38,6 +38,7 @@
 #include <cpu/x86/smm.h>
 #include "pch.h"
 #include "nvs.h"
+#include <southbridge/intel/common/pciehp.h>
 
 #define NMI_OFF	0
 
@@ -838,6 +839,14 @@
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+
+	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -848,6 +857,7 @@
 	.enable_resources	= pch_lpc_enable_resources,
 	.write_acpi_tables      = acpi_write_hpet,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 	.init			= lpc_init,
 	.enable			= pch_lpc_enable,
 	.scan_bus		= scan_static_bus,