Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
| 27 | #include <pc80/i8259.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <arch/ioapic.h> |
| 30 | #include <arch/acpi.h> |
| 31 | #include <cpu/cpu.h> |
| 32 | #include "pch.h" |
| 33 | |
| 34 | #define NMI_OFF 0 |
| 35 | |
| 36 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
| 37 | #define TEST_SMM_FLASH_LOCKDOWN 0 |
| 38 | |
| 39 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 40 | |
| 41 | static void pch_enable_apic(struct device *dev) |
| 42 | { |
| 43 | int i; |
| 44 | u32 reg32; |
| 45 | volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); |
| 46 | volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); |
| 47 | |
| 48 | /* Enable ACPI I/O and power management. |
| 49 | * Set SCI IRQ to IRQ9 |
| 50 | */ |
| 51 | pci_write_config8(dev, ACPI_CNTL, 0x80); |
| 52 | |
| 53 | *ioapic_index = 0; |
| 54 | *ioapic_data = (1 << 25); |
| 55 | |
| 56 | /* affirm full set of redirection table entries ("write once") */ |
| 57 | *ioapic_index = 1; |
| 58 | reg32 = *ioapic_data; |
| 59 | *ioapic_index = 1; |
| 60 | *ioapic_data = reg32; |
| 61 | |
| 62 | *ioapic_index = 0; |
| 63 | reg32 = *ioapic_data; |
| 64 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); |
| 65 | if (reg32 != (1 << 25)) |
| 66 | die("APIC Error\n"); |
| 67 | |
| 68 | printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); |
| 69 | for (i=0; i<3; i++) { |
| 70 | *ioapic_index = i; |
| 71 | printk(BIOS_SPEW, " reg 0x%04x:", i); |
| 72 | reg32 = *ioapic_data; |
| 73 | printk(BIOS_SPEW, " 0x%08x\n", reg32); |
| 74 | } |
| 75 | |
| 76 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 77 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
| 78 | } |
| 79 | |
| 80 | static void pch_enable_serial_irqs(struct device *dev) |
| 81 | { |
| 82 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 83 | pci_write_config8(dev, SERIRQ_CNTL, |
| 84 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 85 | #if !CONFIG_SERIRQ_CONTINUOUS_MODE |
| 86 | pci_write_config8(dev, SERIRQ_CNTL, |
| 87 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 88 | #endif |
| 89 | } |
| 90 | |
| 91 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 92 | * 0x00 - 0000 = Reserved |
| 93 | * 0x01 - 0001 = Reserved |
| 94 | * 0x02 - 0010 = Reserved |
| 95 | * 0x03 - 0011 = IRQ3 |
| 96 | * 0x04 - 0100 = IRQ4 |
| 97 | * 0x05 - 0101 = IRQ5 |
| 98 | * 0x06 - 0110 = IRQ6 |
| 99 | * 0x07 - 0111 = IRQ7 |
| 100 | * 0x08 - 1000 = Reserved |
| 101 | * 0x09 - 1001 = IRQ9 |
| 102 | * 0x0A - 1010 = IRQ10 |
| 103 | * 0x0B - 1011 = IRQ11 |
| 104 | * 0x0C - 1100 = IRQ12 |
| 105 | * 0x0D - 1101 = Reserved |
| 106 | * 0x0E - 1110 = IRQ14 |
| 107 | * 0x0F - 1111 = IRQ15 |
| 108 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 109 | * 0x80 - The PIRQ is not routed. |
| 110 | */ |
| 111 | |
| 112 | static void pch_pirq_init(device_t dev) |
| 113 | { |
| 114 | device_t irq_dev; |
| 115 | /* Get the chip configuration */ |
| 116 | config_t *config = dev->chip_info; |
| 117 | |
| 118 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 119 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 120 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 121 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 122 | |
| 123 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 124 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 125 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 126 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 127 | |
| 128 | /* Eric Biederman once said we should let the OS do this. |
| 129 | * I am not so sure anymore he was right. |
| 130 | */ |
| 131 | |
| 132 | for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 133 | u8 int_pin=0, int_line=0; |
| 134 | |
| 135 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 136 | continue; |
| 137 | |
| 138 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 139 | |
| 140 | switch (int_pin) { |
| 141 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 142 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 143 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 144 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 145 | } |
| 146 | |
| 147 | if (!int_line) |
| 148 | continue; |
| 149 | |
| 150 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | static void pch_gpi_routing(device_t dev) |
| 155 | { |
| 156 | /* Get the chip configuration */ |
| 157 | config_t *config = dev->chip_info; |
| 158 | u32 reg32 = 0; |
| 159 | |
| 160 | /* An array would be much nicer here, or some |
| 161 | * other method of doing this. |
| 162 | */ |
| 163 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 164 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 165 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 166 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 167 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 168 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 169 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 170 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 171 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 172 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 173 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 174 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 175 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 176 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 177 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 178 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 179 | |
| 180 | pci_write_config32(dev, 0xb8, reg32); |
| 181 | } |
| 182 | |
| 183 | static void pch_power_options(device_t dev) |
| 184 | { |
| 185 | u8 reg8; |
| 186 | u16 reg16, pmbase; |
| 187 | u32 reg32; |
| 188 | const char *state; |
| 189 | /* Get the chip configuration */ |
| 190 | config_t *config = dev->chip_info; |
| 191 | |
| 192 | int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 193 | int nmi_option; |
| 194 | |
| 195 | /* Which state do we want to goto after g3 (power restored)? |
| 196 | * 0 == S0 Full On |
| 197 | * 1 == S5 Soft Off |
| 198 | * |
| 199 | * If the option is not existent (Laptops), use Kconfig setting. |
| 200 | */ |
| 201 | get_option(&pwr_on, "power_on_after_fail"); |
| 202 | |
| 203 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 204 | reg16 &= 0xfffe; |
| 205 | switch (pwr_on) { |
| 206 | case MAINBOARD_POWER_OFF: |
| 207 | reg16 |= 1; |
| 208 | state = "off"; |
| 209 | break; |
| 210 | case MAINBOARD_POWER_ON: |
| 211 | reg16 &= ~1; |
| 212 | state = "on"; |
| 213 | break; |
| 214 | case MAINBOARD_POWER_KEEP: |
| 215 | reg16 &= ~1; |
| 216 | state = "state keep"; |
| 217 | break; |
| 218 | default: |
| 219 | state = "undefined"; |
| 220 | } |
| 221 | |
| 222 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 223 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 224 | |
| 225 | reg16 &= ~(1 << 10); |
| 226 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 227 | |
| 228 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 229 | |
| 230 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 231 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 232 | |
| 233 | /* Set up NMI on errors. */ |
| 234 | reg8 = inb(0x61); |
| 235 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 236 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 237 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 238 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 239 | outb(reg8, 0x61); |
| 240 | |
| 241 | reg8 = inb(0x70); |
| 242 | nmi_option = NMI_OFF; |
| 243 | get_option(&nmi_option, "nmi"); |
| 244 | if (nmi_option) { |
| 245 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 246 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 247 | } else { |
| 248 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
| 249 | reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
| 250 | } |
| 251 | outb(reg8, 0x70); |
| 252 | |
| 253 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 254 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 255 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 256 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
| 257 | #if DEBUG_PERIODIC_SMIS |
| 258 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 259 | * periodic SMIs. |
| 260 | */ |
| 261 | reg16 |= (3 << 0); // Periodic SMI every 8s |
| 262 | #endif |
| 263 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 264 | |
| 265 | // Set the board's GPI routing. |
| 266 | pch_gpi_routing(dev); |
| 267 | |
| 268 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 269 | |
| 270 | outl(config->gpe0_en, pmbase + GPE0_EN); |
| 271 | outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); |
| 272 | |
| 273 | /* Set up power management block and determine sleep mode */ |
| 274 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 275 | reg32 &= ~(7 << 10); // SLP_TYP |
| 276 | reg32 |= (1 << 0); // SCI_EN |
| 277 | outl(reg32, pmbase + 0x04); |
| 278 | |
| 279 | /* Clear magic status bits to prevent unexpected wake */ |
| 280 | reg32 = RCBA32(0x3310); |
| 281 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 282 | RCBA32(0x3310) = reg32; |
| 283 | |
| 284 | reg32 = RCBA32(0x3f02); |
| 285 | reg32 &= ~0xf; |
| 286 | RCBA32(0x3f02) = reg32; |
| 287 | } |
| 288 | |
| 289 | static void pch_rtc_init(struct device *dev) |
| 290 | { |
| 291 | u8 reg8; |
| 292 | int rtc_failed; |
| 293 | |
| 294 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 295 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 296 | if (rtc_failed) { |
| 297 | reg8 &= ~RTC_BATTERY_DEAD; |
| 298 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 299 | } |
| 300 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 301 | |
| 302 | rtc_init(rtc_failed); |
| 303 | } |
| 304 | |
| 305 | static void pch_pm_init(struct device *dev) |
| 306 | { |
| 307 | pci_write_config8(dev, 0xa9, 0x47); |
| 308 | RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); |
| 309 | RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); |
| 310 | RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); |
| 311 | RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); |
| 312 | RCBA32(0x2304) = 0xc0388400; |
| 313 | RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); |
| 314 | RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); |
| 315 | RCBA32_AND_OR(0x3314, ~0x1f, 0xf); |
| 316 | RCBA32(0x3318) = 0x050f0000; |
| 317 | RCBA32(0x3324) = 0x04000000; |
| 318 | RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); |
| 319 | RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); |
| 320 | RCBA32(0x3360) = 0x0001c000; |
| 321 | RCBA32(0x3368) = 0x00061100; |
| 322 | RCBA32(0x3378) = 0x7f8fdfff; |
| 323 | RCBA32(0x337c) = 0x000003fc; |
| 324 | RCBA32(0x3388) = 0x00001000; |
| 325 | RCBA32(0x3390) = 0x0001c000; |
| 326 | RCBA32(0x33a0) = 0x00000800; |
| 327 | RCBA32(0x33b0) = 0x00001000; |
| 328 | RCBA32(0x33c0) = 0x00093900; |
| 329 | RCBA32(0x33cc) = 0x24653002; |
| 330 | RCBA32(0x33d0) = 0x062108fe; |
| 331 | RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); |
| 332 | RCBA32(0x3a28) = 0x01010000; |
| 333 | RCBA32(0x3a2c) = 0x01010404; |
| 334 | RCBA32(0x3a80) = 0x01041041; |
| 335 | RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); |
| 336 | RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ |
| 337 | RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ |
| 338 | RCBA32(0x3a6c) = 0x00000001; |
| 339 | RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); |
| 340 | RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); |
| 341 | RCBA32(0x33c8) = 0; |
| 342 | RCBA32_AND_OR(0x21b0, ~0UL, 0xf); |
| 343 | } |
| 344 | |
| 345 | static void enable_hpet(void) |
| 346 | { |
| 347 | u32 reg32; |
| 348 | |
| 349 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 350 | reg32 = RCBA32(HPTC); |
| 351 | reg32 |= (1 << 7); // HPET Address Enable |
| 352 | reg32 &= ~(3 << 0); |
| 353 | RCBA32(HPTC) = reg32; |
| 354 | } |
| 355 | |
| 356 | static void enable_clock_gating(device_t dev) |
| 357 | { |
| 358 | u32 reg32; |
| 359 | u16 reg16; |
| 360 | |
| 361 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 362 | |
| 363 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 364 | reg16 |= (1 << 2) | (1 << 11); |
| 365 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 366 | |
| 367 | pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); |
| 368 | pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); |
| 369 | pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); |
| 370 | pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); |
| 371 | |
| 372 | reg32 = RCBA32(CG); |
| 373 | reg32 |= (1 << 31); |
| 374 | reg32 |= (1 << 29) | (1 << 28); |
| 375 | reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); |
| 376 | reg32 |= (1 << 16); |
| 377 | reg32 |= (1 << 17); |
| 378 | reg32 |= (1 << 18); |
| 379 | reg32 |= (1 << 22); |
| 380 | reg32 |= (1 << 23); |
| 381 | reg32 &= ~(1 << 20); |
| 382 | reg32 |= (1 << 19); |
| 383 | reg32 |= (1 << 0); |
| 384 | reg32 |= (0xf << 1); |
| 385 | RCBA32(CG) = reg32; |
| 386 | |
| 387 | RCBA32_OR(0x38c0, 0x7); |
| 388 | RCBA32_OR(0x36d4, 0x6680c004); |
| 389 | RCBA32_OR(0x3564, 0x3); |
| 390 | } |
| 391 | |
| 392 | #if CONFIG_HAVE_SMI_HANDLER |
| 393 | static void pch_lock_smm(struct device *dev) |
| 394 | { |
| 395 | #if TEST_SMM_FLASH_LOCKDOWN |
| 396 | u8 reg8; |
| 397 | #endif |
| 398 | |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 399 | if (acpi_slp_type != 3) { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 400 | #if ENABLE_ACPI_MODE_IN_COREBOOT |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 401 | printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); |
| 402 | outb(0xe1, 0xb2); // Enable ACPI mode |
| 403 | printk(BIOS_DEBUG, "done.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 404 | #else |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 405 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
| 406 | outb(0x1e, 0xb2); // Disable ACPI mode |
| 407 | printk(BIOS_DEBUG, "done.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 408 | #endif |
Duncan Laurie | 95be1d6 | 2012-04-09 12:31:43 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 411 | /* Don't allow evil boot loaders, kernels, or |
| 412 | * userspace applications to deceive us: |
| 413 | */ |
| 414 | smm_lock(); |
| 415 | |
| 416 | #if TEST_SMM_FLASH_LOCKDOWN |
| 417 | /* Now try this: */ |
| 418 | printk(BIOS_DEBUG, "Locking BIOS to RO... "); |
| 419 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 420 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 421 | (reg8&1)?"rw":"ro"); |
| 422 | reg8 &= ~(1 << 0); /* clear BIOSWE */ |
| 423 | pci_write_config8(dev, 0xdc, reg8); |
| 424 | reg8 |= (1 << 1); /* set BLE */ |
| 425 | pci_write_config8(dev, 0xdc, reg8); |
| 426 | printk(BIOS_DEBUG, "ok.\n"); |
| 427 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 428 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 429 | (reg8&1)?"rw":"ro"); |
| 430 | |
| 431 | printk(BIOS_DEBUG, "Writing:\n"); |
| 432 | *(volatile u8 *)0xfff00000 = 0x00; |
| 433 | printk(BIOS_DEBUG, "Testing:\n"); |
| 434 | reg8 |= (1 << 0); /* set BIOSWE */ |
| 435 | pci_write_config8(dev, 0xdc, reg8); |
| 436 | |
| 437 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 438 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 439 | (reg8&1)?"rw":"ro"); |
| 440 | printk(BIOS_DEBUG, "Done.\n"); |
| 441 | #endif |
| 442 | } |
| 443 | #endif |
| 444 | |
| 445 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 446 | { |
| 447 | u8 reg8; |
| 448 | |
| 449 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
| 450 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 451 | reg8 &= ~(1 << 5); |
| 452 | pci_write_config8(dev, 0xdc, reg8); |
| 453 | } |
| 454 | |
| 455 | static void pch_fixups(struct device *dev) |
| 456 | { |
| 457 | u8 gen_pmcon_2; |
| 458 | |
| 459 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 460 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 461 | gen_pmcon_2 |= (1 << 7); |
| 462 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 463 | |
| 464 | /* |
| 465 | * Enable DMI ASPM in the PCH |
| 466 | */ |
| 467 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 468 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 469 | RCBA32_OR(0x21a8, 0x3); |
| 470 | } |
| 471 | |
| 472 | static void pch_decode_init(struct device *dev) |
| 473 | { |
| 474 | config_t *config = dev->chip_info; |
| 475 | |
| 476 | printk(BIOS_DEBUG, "pch_decode_init\n"); |
| 477 | |
| 478 | pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); |
| 479 | pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); |
| 480 | pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); |
| 481 | pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); |
| 482 | } |
| 483 | |
| 484 | static void lpc_init(struct device *dev) |
| 485 | { |
| 486 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 487 | |
| 488 | /* Set the value for PCI command register. */ |
| 489 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 490 | |
| 491 | /* IO APIC initialization. */ |
| 492 | pch_enable_apic(dev); |
| 493 | |
| 494 | pch_enable_serial_irqs(dev); |
| 495 | |
| 496 | /* Setup the PIRQ. */ |
| 497 | pch_pirq_init(dev); |
| 498 | |
| 499 | /* Setup power options. */ |
| 500 | pch_power_options(dev); |
| 501 | |
| 502 | /* Initialize power management */ |
| 503 | pch_pm_init(dev); |
| 504 | |
| 505 | /* Set the state of the GPIO lines. */ |
| 506 | //gpio_init(dev); |
| 507 | |
| 508 | /* Initialize the real time clock. */ |
| 509 | pch_rtc_init(dev); |
| 510 | |
| 511 | /* Initialize ISA DMA. */ |
| 512 | isa_dma_init(); |
| 513 | |
| 514 | /* Initialize the High Precision Event Timers, if present. */ |
| 515 | enable_hpet(); |
| 516 | |
| 517 | /* Initialize Clock Gating */ |
| 518 | enable_clock_gating(dev); |
| 519 | |
| 520 | setup_i8259(); |
| 521 | |
| 522 | /* The OS should do this? */ |
| 523 | /* Interrupt 9 should be level triggered (SCI) */ |
| 524 | i8259_configure_irq_trigger(9, 1); |
| 525 | |
| 526 | pch_disable_smm_only_flashing(dev); |
| 527 | |
| 528 | #if CONFIG_HAVE_SMI_HANDLER |
| 529 | pch_lock_smm(dev); |
| 530 | #endif |
| 531 | |
| 532 | pch_fixups(dev); |
| 533 | } |
| 534 | |
| 535 | static void pch_lpc_read_resources(device_t dev) |
| 536 | { |
| 537 | struct resource *res; |
| 538 | |
| 539 | /* Get the normal PCI resources of this device. */ |
| 540 | pci_dev_read_resources(dev); |
| 541 | |
| 542 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 543 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 544 | res->base = 0; |
| 545 | res->size = 0x1000; |
| 546 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 547 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 548 | |
| 549 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 550 | res->base = 0xff800000; |
| 551 | res->size = 0x00800000; /* 8 MB for flash */ |
| 552 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 553 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 554 | |
| 555 | res = new_resource(dev, 3); /* IOAPIC */ |
| 556 | res->base = IO_APIC_ADDR; |
| 557 | res->size = 0x00001000; |
| 558 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 559 | } |
| 560 | |
| 561 | static void pch_lpc_enable_resources(device_t dev) |
| 562 | { |
| 563 | pch_decode_init(dev); |
| 564 | return pci_dev_enable_resources(dev); |
| 565 | } |
| 566 | |
| 567 | static void pch_lpc_enable(device_t dev) |
| 568 | { |
| 569 | /* Enable PCH Display Port */ |
| 570 | RCBA16(DISPBDF) = 0x0010; |
| 571 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 572 | |
| 573 | pch_enable(dev); |
| 574 | } |
| 575 | |
| 576 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 577 | { |
| 578 | if (!vendor || !device) { |
| 579 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 580 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 581 | } else { |
| 582 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 583 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | static struct pci_operations pci_ops = { |
| 588 | .set_subsystem = set_subsystem, |
| 589 | }; |
| 590 | |
| 591 | static struct device_operations device_ops = { |
| 592 | .read_resources = pch_lpc_read_resources, |
| 593 | .set_resources = pci_dev_set_resources, |
| 594 | .enable_resources = pch_lpc_enable_resources, |
| 595 | .init = lpc_init, |
| 596 | .enable = pch_lpc_enable, |
| 597 | .scan_bus = scan_static_bus, |
| 598 | .ops_pci = &pci_ops, |
| 599 | }; |
| 600 | |
| 601 | |
| 602 | /* IDs for LPC device of Intel 6 series Chipset and |
| 603 | * Intel C200 Series Chipset according to specification |
| 604 | * update from August 2011 |
| 605 | */ |
| 606 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame^] | 607 | static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, |
| 608 | 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, |
| 609 | 0x1c4f, 0x1c50, 0x1c52, 0x1c54, |
| 610 | 0x1e55, 0x1c56, 0x1c5c, 0x1e5d, |
| 611 | 0x1e5e, 0x1e5f, |
| 612 | 0 }; |
| 613 | |
| 614 | static const struct pci_driver pch_lpc __pci_driver = { |
| 615 | .ops = &device_ops, |
| 616 | .vendor = PCI_VENDOR_ID_INTEL, |
| 617 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 618 | }; |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame^] | 619 | |
| 620 | |