Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 1 | #ifndef CPU_AMD_GX2DEF_H |
| 2 | #define CPU_AMD_GX2DEF_H |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 3 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 4 | #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ |
| 5 | #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ |
| 6 | #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ |
| 7 | #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 8 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 9 | #define CPU_REV_1_0 0x011 |
| 10 | #define CPU_REV_1_1 0x012 |
| 11 | #define CPU_REV_1_2 0x013 |
| 12 | #define CPU_REV_1_3 0x014 |
| 13 | #define CPU_REV_2_0 0x020 |
| 14 | #define CPU_REV_2_1 0x021 |
| 15 | #define CPU_REV_2_2 0x022 |
| 16 | #define CPU_REV_3_0 0x030 |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 17 | |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 18 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */ |
| 19 | #define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08) |
| 20 | #define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09) |
| 21 | #define GLCP_DBGOUT (MSR_GLCP + 0x0C) |
| 22 | #define GLCP_PROCSTAT (MSR_GLCP + 0x0D) |
| 23 | #define GLCP_DBGCLKCTL (MSR_GLCP + 0x16) |
| 24 | #define GLCP_CHIP_REVID (MSR_GLCP + 0x17) |
| 25 | #define GLCP_TH_OD (MSR_GLCP + 0x1E) |
| 26 | #define GLCP_FIFOCTL (MSR_GLCP + 0x5E) |
Li-Ta Lo | af9484a | 2006-03-20 21:18:53 +0000 | [diff] [blame] | 27 | |
| 28 | /* GLCP_SYS_RSTPLL, Upper 32 bits */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 29 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 30 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 31 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
Li-Ta Lo | af9484a | 2006-03-20 21:18:53 +0000 | [diff] [blame] | 32 | |
| 33 | /* GLCP_SYS_RSTPLL, Lower 32 bits */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 34 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 35 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 36 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 37 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 38 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 39 | #define GLCP_SYS_RSTPLL_PD 14 |
| 40 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 41 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 42 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 43 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 44 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
Li-Ta Lo | af9484a | 2006-03-20 21:18:53 +0000 | [diff] [blame] | 45 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 46 | /* MSR routing as follows */ |
| 47 | /* MSB = 1 means not for CPU */ |
| 48 | /* next 3 bits 1st port */ |
| 49 | /* next3 bits next port if through an GLIU */ |
| 50 | /* etc... */ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 51 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 52 | /* Redcloud as follows. */ |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 53 | /* GLIU0*/ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 54 | /* port0 - GLIU0 */ |
| 55 | /* port1 - MC */ |
| 56 | /* port2 - GLIU1 */ |
| 57 | /* port3 - CPU */ |
| 58 | /* port4 - VG */ |
| 59 | /* port5 - GP */ |
| 60 | /* port6 - DF */ |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 61 | |
| 62 | /* GLIU1*/ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 63 | /* port1 - GLIU0 */ |
| 64 | /* port3 - GLCP */ |
| 65 | /* port4 - PCI */ |
| 66 | /* port5 - FG */ |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 67 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 68 | #define GL0_GLIU0 0 |
| 69 | #define GL0_MC 1 |
| 70 | #define GL0_GLIU1 2 |
| 71 | #define GL0_CPU 3 |
| 72 | #define GL0_VG 4 |
| 73 | #define GL0_GP 5 |
| 74 | #define GL0_DF 6 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 75 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 76 | #define GL1_GLIU0 1 |
| 77 | #define GL1_GLCP 3 |
| 78 | #define GL1_PCI 4 |
| 79 | #define GL1_FG 5 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 80 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 81 | #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ |
| 82 | #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ |
| 83 | #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ |
| 84 | #define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ |
| 85 | #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ |
| 86 | #define MSR_GP (GL0_GP << 29) /* A000xxxx */ |
| 87 | #define MSR_DF (GL0_DF << 29) /* C000xxxx */ |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 88 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 89 | #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ |
| 90 | #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ |
| 91 | #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 92 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 93 | /* GeodeLink Interface Unit 0 (GLIU0) port0 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 94 | #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) |
| 95 | #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 96 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 97 | #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) |
| 98 | #define GLIU0_CAP (MSR_GLIU0 + 0x86) |
| 99 | #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 100 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 101 | /* Memory Controller GLIU0 port 1 */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 102 | #define MC_GLD_MSR_CAP (MSR_MC + 0x2000) |
| 103 | #define MC_GLD_MSR_PM (MSR_MC + 0x2004) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 104 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 105 | #define MC_CF07_DATA (MSR_MC + 0x18) |
| 106 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 107 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 108 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 109 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 110 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 111 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 112 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 113 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 114 | #define CF07_LOWER_REF_INT_SHIFT 8 |
| 115 | #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) |
| 116 | #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) |
| 117 | #define CF07_LOWER_EMR_QFC_SET (1 << 26) |
| 118 | #define CF07_LOWER_EMR_DRV_SET (1 << 25) |
| 119 | #define CF07_LOWER_REF_TEST_SET (1 << 3) |
| 120 | #define CF07_LOWER_PROG_DRAM_SET (1 << 0) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 121 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 122 | #define MC_CF8F_DATA (MSR_MC + 0x19) |
| 123 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 124 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 125 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 126 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 127 | #define CF8F_UPPER_REORDER_DIS_SET (1 << 8) |
| 128 | #define CF8F_UPPER_REG_DIMM_SHIFT 4 |
| 129 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
| 130 | #define CF8F_LOWER_REF2ACT_SHIFT 24 |
| 131 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 132 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 133 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 134 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
| 135 | #define CF8F_UPPER_32BIT_SET (1 << 5) |
| 136 | #define CF8F_UPPER_HOI_LOI_SET (1 << 1) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 137 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 138 | #define MC_CF1017_DATA (MSR_MC + 0x1A) |
| 139 | #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) |
| 140 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 141 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 142 | #define MC_CFCLK_DBUG (MSR_MC + 0x1D) |
| 143 | #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) |
| 144 | #define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) |
| 145 | #define CFCLK_UPPER_MTEST_EN_SET (1 << 0) |
| 146 | #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) |
| 147 | #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) |
| 148 | #define CFCLK_LOWER_SDCLK_SET (0x0F << 0) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 149 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 150 | #define MC_CF_RDSYNC (MSR_MC + 0x1F) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 151 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 152 | /* GLIU1 GLIU0 port2 */ |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 153 | #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) |
| 154 | #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 155 | #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 156 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 157 | /* CPU ; does not need routing instructions since we are executing there. */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 158 | #define CPU_GLD_MSR_CAP 0x2000 |
| 159 | #define CPU_GLD_MSR_CONFIG 0x2001 |
| 160 | #define CPU_GLD_MSR_PM 0x2004 |
| 161 | #define CPU_GLD_MSR_DIAG 0x2005 |
| 162 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 163 | #define DIAG_SEL1_SET (1 << 31) |
| 164 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 165 | #define DIAG_SET0_SET (1 << 15) |
| 166 | #define CPU_PF_BTB_CONF 0x1100 |
| 167 | #define BTB_ENABLE_SET (1 << 0) |
| 168 | #define RETURN_STACK_ENABLE_SET (1 << 4) |
| 169 | #define CPU_PF_BTBRMA_BIST 0x110C |
| 170 | #define CPU_XC_CONFIG 0x1210 |
| 171 | #define XC_CONFIG_SUSP_ON_HLT (1 << 0) |
| 172 | #define CPU_ID_CONFIG 0x1250 |
| 173 | #define ID_CONFIG_SERIAL_SET (1 << 0) |
| 174 | #define CPU_AC_MSR 0x1301 |
| 175 | #define CPU_EX_BIST 0x1428 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 176 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 177 | /* IM */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 178 | #define CPU_IM_CONFIG 0x1700 |
| 179 | #define IM_CONFIG_LOWER_ICD_SET (1 << 8) |
| 180 | #define IM_CONFIG_LOWER_QWT_SET (1 << 20) |
| 181 | #define CPU_IC_INDEX 0x1710 |
| 182 | #define CPU_IC_DATA 0x1711 |
| 183 | #define CPU_IC_TAG 0x1712 |
| 184 | #define CPU_IC_TAG_I 0x1713 |
| 185 | #define CPU_ITB_INDEX 0x1720 |
| 186 | #define CPU_ITB_LRU 0x1721 |
| 187 | #define CPU_ITB_ENTRY 0x1722 |
| 188 | #define CPU_ITB_ENTRY_I 0x1723 |
| 189 | #define CPU_IM_BIST_TAG 0x1730 |
| 190 | #define CPU_IM_BIST_DATA 0x1731 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 191 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 192 | /* various CPU MSRs */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 193 | #define CPU_DM_CONFIG0 0x1800 |
| 194 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
| 195 | #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) |
| 196 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
| 197 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 198 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 199 | /* configuration MSRs */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 200 | #define CPU_RCONF_DEFAULT 0x1808 |
| 201 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 202 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 203 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 204 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 205 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 206 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 207 | #define CPU_RCONF_BYPASS 0x180A |
| 208 | #define CPU_RCONF_A0_BF 0x180B |
| 209 | #define CPU_RCONF_C0_DF 0x180C |
| 210 | #define CPU_RCONF_E0_FF 0x180D |
| 211 | #define CPU_RCONF_SMM 0x180E |
| 212 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 213 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 214 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 215 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 216 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 217 | #define CPU_RCONF_DMM 0x180F |
| 218 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 219 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 220 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 221 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 222 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 223 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 224 | #define CPU_RCONF0 0x1810 |
| 225 | #define CPU_RCONF1 0x1811 |
| 226 | #define CPU_RCONF2 0x1812 |
| 227 | #define CPU_RCONF3 0x1813 |
| 228 | #define CPU_RCONF4 0x1814 |
| 229 | #define CPU_RCONF5 0x1815 |
| 230 | #define CPU_RCONF6 0x1816 |
| 231 | #define CPU_RCONF7 0x1817 |
| 232 | #define CPU_CR1_MSR 0x1881 |
| 233 | #define CPU_CR2_MSR 0x1882 |
| 234 | #define CPU_CR3_MSR 0x1883 |
| 235 | #define CPU_CR4_MSR 0x1884 |
| 236 | #define CPU_DC_INDEX 0x1890 |
| 237 | #define CPU_DC_DATA 0x1891 |
| 238 | #define CPU_DC_TAG 0x1892 |
| 239 | #define CPU_DC_TAG_I 0x1893 |
| 240 | #define CPU_SNOOP 0x1894 |
| 241 | #define CPU_DTB_INDEX 0x1898 |
| 242 | #define CPU_DTB_LRU 0x1899 |
| 243 | #define CPU_DTB_ENTRY 0x189A |
| 244 | #define CPU_DTB_ENTRY_I 0x189B |
| 245 | #define CPU_L2TB_INDEX 0x189C |
| 246 | #define CPU_L2TB_LRU 0x189D |
| 247 | #define CPU_L2TB_ENTRY 0x189E |
| 248 | #define CPU_L2TB_ENTRY_I 0x189F |
| 249 | #define CPU_DM_BIST 0x18C0 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 250 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 251 | /* SMM */ |
| 252 | #define CPU_AC_SMM_CTL 0x1301 |
| 253 | #define SMM_NMI_EN_SET (1<<0) |
| 254 | #define SMM_SUSP_EN_SET (1<<1) |
| 255 | #define NEST_SMI_EN_SET (1<<2) |
| 256 | #define SMM_INST_EN_SET (1<<3) |
| 257 | #define INTL_SMI_EN_SET (1<<4) |
| 258 | #define EXTL_SMI_EN_SET (1<<5) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 259 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 260 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 261 | #define FPU_IE_SET (1<<0) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 262 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 263 | #define CPU_FP_UROM_BIST 0x1A03 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 264 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 265 | #define CPU_BC_CONF_0 0x1900 |
| 266 | #define TSC_SUSP_SET (1<<5) |
| 267 | #define SUSP_EN_SET (1<<12) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 268 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 269 | /* VG GLIU0 port4 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 270 | #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) |
| 271 | #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) |
| 272 | #define VG_GLD_MSR_PM (MSR_VG + 0x2004) |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 273 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 274 | #define GP_GLD_MSR_CAP (MSR_GP + 0x2000) |
| 275 | #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) |
| 276 | #define GP_GLD_MSR_PM (MSR_GP + 0x2004) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 277 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 278 | /* DF GLIU0 port6 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 279 | #define DF_GLD_MSR_CAP (MSR_DF + 0x2000) |
| 280 | #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) |
| 281 | #define DF_LOWER_LCD_SHIFT 6 |
| 282 | #define DF_GLD_MSR_PM (MSR_DF + 0x2004) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 283 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 284 | /* GeodeLink Control Processor GLIU1 port3 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 285 | #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) |
| 286 | #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) |
| 287 | #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 288 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 289 | #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 290 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 291 | #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */) |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 292 | #define RSTPLL_UPPER_MDIV_SHIFT 9 |
| 293 | #define RSTPLL_UPPER_VDIV_SHIFT 6 |
| 294 | #define RSTPLL_UPPER_FBDIV_SHIFT 0 |
| 295 | #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 |
| 296 | #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) |
| 297 | #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 |
| 298 | #define RSTPPL_LOWER_BYPASS_SHIFT 15 |
| 299 | #define RSTPPL_LOWER_TST_SHIFT 11 |
| 300 | #define RSTPPL_LOWER_SDRMODE_SHIFT 10 |
| 301 | #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 |
| 302 | #define RSTPPL_LOWER_LOCK_SET (1<<25) |
| 303 | #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) |
| 304 | #define RSTPPL_LOWER_BYPASS_SET (1<<15) |
| 305 | #define RSTPPL_LOWER_PD_SET (1<<14) |
| 306 | #define RSTPPL_LOWER_PLL_RESET_SET (1<<13) |
| 307 | #define RSTPPL_LOWER_SDRMODE_SET (1<<10) |
| 308 | #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) |
| 309 | #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) |
| 310 | #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 311 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 312 | #define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */) |
| 313 | #define DOTPPL_LOWER_PD_SET (1<<14) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 314 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 315 | /* GLIU1 port 4 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 316 | #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) |
| 317 | #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) |
| 318 | #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 319 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 320 | #define GLPCI_CTRL (MSR_PCI + 0x2010) |
| 321 | #define GLPCI_CTRL_UPPER_FTH_SHIFT 28 |
| 322 | #define GLPCI_CTRL_UPPER_RTH_SHIFT 24 |
| 323 | #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 |
| 324 | #define GLPCI_CTRL_UPPER_DTL_SHIFT 14 |
| 325 | #define GLPCI_CTRL_UPPER_WTO_SHIFT 11 |
| 326 | #define GLPCI_CTRL_UPPER_LAT_SHIFT 3 |
| 327 | #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 |
| 328 | #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 |
| 329 | #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 |
| 330 | #define GLPCI_CTRL_LOWER_ER_SET (1<<11) |
| 331 | #define GLPCI_CTRL_LOWER_LDE_SET (1<<9) |
| 332 | #define GLPCI_CTRL_LOWER_OWC_SET (1<<4) |
| 333 | #define GLPCI_CTRL_LOWER_IWC_SET (1<<3) |
| 334 | #define GLPCI_CTRL_LOWER_PCD_SET (1<<2) |
| 335 | #define GLPCI_CTRL_LOWER_ME_SET (1<<0) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 336 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 337 | #define GLPCI_ARB (MSR_PCI + 0x2011) |
| 338 | #define GLPCI_ARB_UPPER_BM1_SET (1<<17) |
| 339 | #define GLPCI_ARB_UPPER_BM0_SET (1<<16) |
| 340 | #define GLPCI_ARB_UPPER_CPRE_SET (1<<15) |
| 341 | #define GLPCI_ARB_UPPER_PRE2_SET (1<<10) |
| 342 | #define GLPCI_ARB_UPPER_PRE1_SET (1<<9) |
| 343 | #define GLPCI_ARB_UPPER_PRE0_SET (1<<8) |
| 344 | #define GLPCI_ARB_UPPER_CRME_SET (1<<7) |
| 345 | #define GLPCI_ARB_UPPER_RME2_SET (1<<2) |
| 346 | #define GLPCI_ARB_UPPER_RME1_SET (1<<1) |
| 347 | #define GLPCI_ARB_UPPER_RME0_SET (1<<0) |
| 348 | #define GLPCI_ARB_LOWER_PRCM_SHIFT 24 |
| 349 | #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 |
| 350 | #define GLPCI_ARB_LOWER_RMT_SHIFT 6 |
| 351 | #define GLPCI_ARB_LOWER_IIE_SET (1<<8) |
| 352 | #define GLPCI_ARB_LOWER_PARK_SET (1<<0) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 353 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 354 | #define GLPCI_REN (MSR_PCI + 0x2014) |
| 355 | #define GLPCI_A0_BF (MSR_PCI + 0x2015) |
| 356 | #define GLPCI_C0_DF (MSR_PCI + 0x2016) |
| 357 | #define GLPCI_E0_FF (MSR_PCI + 0x2017) |
| 358 | #define GLPCI_RC0 (MSR_PCI + 0x2018) |
| 359 | #define GLPCI_RC1 (MSR_PCI + 0x2019) |
| 360 | #define GLPCI_RC2 (MSR_PCI + 0x201A) |
| 361 | #define GLPCI_RC3 (MSR_PCI + 0x201B) |
| 362 | #define GLPCI_RC4 (MSR_PCI + 0x201C) |
| 363 | #define GLPCI_RC_UPPER_TOP_SHIFT 12 |
| 364 | #define GLPCI_RC_LOWER_BASE_SHIFT 12 |
| 365 | #define GLPCI_RC_LOWER_EN_SET (1<<8) |
| 366 | #define GLPCI_RC_LOWER_PF_SET (1<<5) |
| 367 | #define GLPCI_RC_LOWER_WC_SET (1<<4) |
| 368 | #define GLPCI_RC_LOWER_WP_SET (1<<2) |
| 369 | #define GLPCI_RC_LOWER_CD_SET (1<<0) |
| 370 | #define GLPCI_ExtMSR (MSR_PCI + 0x201E) |
| 371 | #define GLPCI_SPARE (MSR_PCI + 0x201F) |
| 372 | #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) |
| 373 | #define GLPCI_SPARE_LOWER_PPD_SET (1<<5) |
| 374 | #define GLPCI_SPARE_LOWER_PPC_SET (1<<4) |
| 375 | #define GLPCI_SPARE_LOWER_MPC_SET (1<<3) |
| 376 | #define GLPCI_SPARE_LOWER_MME_SET (1<<2) |
| 377 | #define GLPCI_SPARE_LOWER_NSE_SET (1<<1) |
| 378 | #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 379 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 380 | /* FooGlue GLIU1 port 5 */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 381 | #define FG_GLD_MSR_CAP (MSR_FG + 0x2000) |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 382 | #define FG_GLD_MSR_CONFIG (MSR_FG + 0x2001) |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 383 | #define FG_GLD_MSR_PM (MSR_FG + 0x2004) |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 384 | #define FG_GIO_MSR_SEL (MSR_FG + 0x2010) |
| 385 | #define FG_BIST (MSR_FG + 0x2005) |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 386 | |
Nils Jacobs | 76890dd | 2010-11-01 15:20:27 +0000 | [diff] [blame] | 387 | /* from MC spec */ |
| 388 | #define MIN_MOD_BANKS 1 |
| 389 | #define MAX_MOD_BANKS 2 |
| 390 | #define MIN_DEV_BANKS 2 |
| 391 | #define MAX_DEV_BANKS 4 |
| 392 | #define MAX_COL_ADDR 17 |
| 393 | |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 394 | /* more fun stuff */ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 395 | #define BM 1 /* Base Mask - map power of 2 size aligned region */ |
| 396 | #define BMO 2 /* BM with an offset */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 397 | #define R 3 /* Range - 4k range minimum */ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 398 | #define RO 4 /* R with offset */ |
| 399 | #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ |
| 400 | #define BMIO 6 /* Base Mask IO */ |
| 401 | #define SCIO 7 /* Swiss 0xCeese IO */ |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame^] | 402 | #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */ |
| 403 | #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */ |
| 404 | #define BMO_SMM 10 /* Special marker for SMM */ |
| 405 | #define BM_SMM 11 /* Special marker for SMM */ |
| 406 | #define BMO_DMM 12 /* Special marker for DMM */ |
| 407 | #define BM_DMM 13 /* Special marker for DMM */ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 408 | #define RO_FB 14 /* special for Frame buffer. */ |
| 409 | #define R_FB 15 /* special for FB. */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 410 | #define OTHER 0x0FE /* Special marker for other */ |
| 411 | #define GL_END 0x0FF /* end */ |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 412 | |
| 413 | #define MSR_GL0 (GL1_GLIU0 << 29) |
| 414 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 415 | /* Set up desc addresses from 20 - E8 */ |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 416 | /* This is chip specific! */ |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 417 | //remove after MSRINIT is gone |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 418 | #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ |
| 419 | #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ |
| 420 | #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ |
| 421 | #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 422 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 423 | #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ |
| 424 | #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ |
| 425 | #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ |
| 426 | #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 427 | |
| 428 | #define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ |
| 429 | #define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ |
| 430 | #define GLIU0_P2D_BM_2 (MSR_GLIU0 + 0x22) |
| 431 | #define GLIU0_P2D_BM_3 (MSR_GLIU0 + 0x23) |
| 432 | #define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) |
| 433 | #define GLIU0_P2D_BM_5 (MSR_GLIU0 + 0x25) |
| 434 | |
| 435 | #define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ |
| 436 | #define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ |
| 437 | |
| 438 | #define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ |
| 439 | |
| 440 | #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) |
| 441 | #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) |
| 442 | #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) |
| 443 | |
| 444 | #define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ |
| 445 | |
| 446 | #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) |
| 447 | #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) |
| 448 | #define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2) |
| 449 | |
| 450 | #define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3) |
| 451 | #define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4) |
| 452 | #define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5) |
| 453 | #define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6) |
| 454 | #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) |
| 455 | #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) |
| 456 | |
| 457 | #define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ |
| 458 | #define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ |
| 459 | #define GLIU1_P2D_BM_2 (MSR_GLIU1 + 0x22) |
| 460 | #define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ |
| 461 | #define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ |
| 462 | #define GLIU1_P2D_BM_5 (MSR_GLIU1 + 0x25) |
| 463 | #define GLIU1_P2D_BM_6 (MSR_GLIU1 + 0x26) |
| 464 | #define GLIU1_P2D_BM_7 (MSR_GLIU1 + 0x27) |
| 465 | #define GLIU1_P2D_BM_8 (MSR_GLIU1 + 0x28) |
| 466 | |
| 467 | #define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ |
| 468 | #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2A) |
| 469 | #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2B) |
| 470 | #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2C) |
| 471 | |
| 472 | #define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ |
| 473 | |
| 474 | #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) |
| 475 | #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) |
| 476 | #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) |
| 477 | |
| 478 | #define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ |
| 479 | #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) |
| 480 | #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) |
| 481 | #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) |
| 482 | #define GLIU1_IOD_SC_4 (MSR_GLIU1 + 0xE7) |
| 483 | #define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8) |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 484 | |
| 485 | /* definitions that are "once you are mostly up, start VSA" type things */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 486 | #define SMM_OFFSET 0x40400000 |
| 487 | #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ |
| 488 | #define DMM_OFFSET 0x0C0000000 |
Ronald G. Minnich | 526b2c4 | 2006-04-10 16:14:19 +0000 | [diff] [blame] | 489 | #define DMM_SIZE 128 |
| 490 | #define FB_OFFSET 0x41000000 |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 491 | #define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ |
| 492 | #define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ |
| 493 | #define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 494 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 495 | #define MDD_SMBUS 0x06000 /* SMBUS IO location */ |
| 496 | #define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ |
| 497 | #define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ |
| 498 | #define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ |
| 499 | #define ACPI_BASE 0x09C00 /* ACPI Base */ |
| 500 | #define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */ |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame] | 501 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 502 | #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ |
| 503 | #define CHIPSET_DEV_NUM 15 |
| 504 | #define IDSEL_BASE 11 /* bit 11 = device 1 */ |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 505 | |
Nils Jacobs | 809e29e | 2010-11-01 14:36:54 +0000 | [diff] [blame] | 506 | /* SB LBAR IO + MEMORY MAP */ |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 507 | #define SMBUS_BASE (0x6000) |
| 508 | #define GPIO_BASE (0x6100) |
| 509 | #define MFGPT_BASE (0x6200) |
| 510 | #define IRQMAP_BASE (0x6300) |
| 511 | #define PMLogic_BASE (0x9D00) |
Ronald G. Minnich | 4b8cf1d | 2006-04-10 23:32:23 +0000 | [diff] [blame] | 512 | |
| 513 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 514 | #if !defined(__ASSEMBLER__) |
Stefan Reinauer | 4292685 | 2010-04-22 10:44:08 +0000 | [diff] [blame] | 515 | #if defined(__PRE_RAM__) |
Nils Jacobs | e474070 | 2010-07-26 23:46:25 +0000 | [diff] [blame] | 516 | void cpuRegInit(void); |
| 517 | void SystemPreInit(void); |
Stefan Reinauer | 4292685 | 2010-04-22 10:44:08 +0000 | [diff] [blame] | 518 | #endif |
Nils Jacobs | e474070 | 2010-07-26 23:46:25 +0000 | [diff] [blame] | 519 | void cpubug(void); |
Stefan Reinauer | 4292685 | 2010-04-22 10:44:08 +0000 | [diff] [blame] | 520 | #endif |
| 521 | |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 522 | #endif /* CPU_AMD_GX2DEF_H */ |