Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 1 | #ifndef CPU_AMD_GX2DEF_H |
| 2 | #define CPU_AMD_GX2DEF_H |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 3 | #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ |
| 4 | #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ |
| 5 | #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ |
| 6 | #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 7 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 8 | #define CPU_REV_1_0 0x011 |
| 9 | #define CPU_REV_1_1 0x012 |
| 10 | #define CPU_REV_1_2 0x013 |
| 11 | #define CPU_REV_1_3 0x014 |
| 12 | #define CPU_REV_2_0 0x020 |
| 13 | #define CPU_REV_2_1 0x021 |
| 14 | #define CPU_REV_2_2 0x022 |
| 15 | #define CPU_REV_3_0 0x030 |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 16 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ |
| 17 | #define GLCP_CLK_DIS_DELAY 0x4c000008 |
| 18 | #define GLCP_PMCLKDISABLE 0x4c000009 |
Li-Ta Lo | af9484a | 2006-03-20 21:18:53 +0000 | [diff] [blame] | 19 | #define GLCP_CHIP_REVID 0x4c000017 |
| 20 | |
| 21 | /* GLCP_SYS_RSTPLL, Upper 32 bits */ |
| 22 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 23 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 24 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
| 25 | |
| 26 | /* GLCP_SYS_RSTPLL, Lower 32 bits */ |
| 27 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 28 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 29 | |
| 30 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 31 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 32 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 33 | #define GLCP_SYS_RSTPLL_PD 14 |
| 34 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 35 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 36 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 37 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 38 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
| 39 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 40 | /* MSR routing as follows*/ |
| 41 | /* MSB = 1 means not for CPU*/ |
| 42 | /* next 3 bits 1st port*/ |
| 43 | /* next3 bits next port if through an GLIU*/ |
| 44 | /* etc...*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 45 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 46 | /*Redcloud as follows.*/ |
| 47 | /* GLIU0*/ |
| 48 | /* port0 - GLIU0*/ |
| 49 | /* port1 - MC*/ |
| 50 | /* port2 - GLIU1*/ |
| 51 | /* port3 - CPU*/ |
| 52 | /* port4 - VG*/ |
| 53 | /* port5 - GP*/ |
| 54 | /* port6 - DF*/ |
| 55 | |
| 56 | /* GLIU1*/ |
| 57 | /* port1 - GLIU0*/ |
| 58 | /* port3 - GLCP*/ |
| 59 | /* port4 - PCI*/ |
| 60 | /* port5 - FG*/ |
| 61 | |
| 62 | |
| 63 | #define GL0_GLIU0 0 |
| 64 | #define GL0_MC 1 |
| 65 | #define GL0_GLIU1 2 |
| 66 | #define GL0_CPU 3 |
| 67 | #define GL0_VG 4 |
| 68 | #define GL0_GP 5 |
| 69 | #define GL0_DF 6 |
| 70 | |
| 71 | #define GL1_GLIU0 1 |
| 72 | #define GL1_GLCP 3 |
| 73 | #define GL1_PCI 4 |
| 74 | #define GL1_FG 5 |
| 75 | |
| 76 | |
| 77 | #define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 78 | #define MSR_MC (GL0_MC << 29) |
| 79 | #define MSR_GLIU1 (GL0_GLIU1 << 29) |
| 80 | #define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/ |
| 81 | #define MSR_VG (GL0_VG << 29) |
| 82 | #define MSR_GP (GL0_GP << 29) |
| 83 | #define MSR_DF (GL0_DF << 29) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 84 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 85 | #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 86 | #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 |
| 87 | #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 |
| 88 | |
| 89 | /* South Bridge*/ |
| 90 | #define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/ |
| 91 | #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ |
| 92 | |
| 93 | |
| 94 | /**/ |
| 95 | /*GeodeLink Interface Unit 0 (GLIU0) port0*/ |
| 96 | /**/ |
| 97 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 98 | #define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 0x2000 |
| 99 | #define GLIU0_GLD_MSR_PM MSR_GLIU0 + 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 100 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 101 | #define GLIU0_DESC_BASE MSR_GLIU0 + 0x20 |
| 102 | #define GLIU0_CAP MSR_GLIU0 + 0x86 |
| 103 | #define GLIU0_GLD_MSR_COH MSR_GLIU0 + 0x80 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 104 | |
| 105 | |
| 106 | /**/ |
| 107 | /* Memory Controller GLIU0 port 1*/ |
| 108 | /**/ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 109 | #define MC_GLD_MSR_CAP MSR_MC + 0x2000 |
| 110 | #define MC_GLD_MSR_PM MSR_MC + 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 111 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 112 | #define MC_CF07_DATA MSR_MC + 0x18 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 113 | |
| 114 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 115 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 116 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 117 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 118 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 119 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 120 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 121 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 122 | |
| 123 | #define CF07_LOWER_REF_INT_SHIFT 8 |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 124 | #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) |
| 125 | #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) |
| 126 | #define CF07_LOWER_EMR_QFC_SET (1 << 26) |
| 127 | #define CF07_LOWER_EMR_DRV_SET (1 << 25) |
| 128 | #define CF07_LOWER_REF_TEST_SET (1 << 3) |
| 129 | #define CF07_LOWER_PROG_DRAM_SET (1 << 0) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 130 | |
| 131 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 132 | #define MC_CF8F_DATA MSR_MC + 0x19 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 133 | |
| 134 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 135 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 136 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 137 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 138 | #define CF8F_UPPER_REORDER_DIS_SET 1 << 8 |
| 139 | #define CF8F_UPPER_REG_DIMM_SHIFT 4 |
| 140 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
| 141 | #define CF8F_LOWER_REF2ACT_SHIFT 24 |
| 142 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 143 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 144 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 145 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
| 146 | #define CF8F_UPPER_32BIT_SET 1 << 5 |
| 147 | #define CF8F_UPPER_HOI_LOI_SET 1 << 1 |
| 148 | |
| 149 | #define MC_CF1017_DATA MSR_MC + 1Ah |
| 150 | |
| 151 | #define CF1017_LOWER_PM1_UP_DLY_SET 1 << 8 |
| 152 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
| 153 | |
| 154 | #define MC_CFCLK_DBUG MSR_MC + 1Dh |
| 155 | |
| 156 | #define CFCLK_UPPER_MTST_B2B_DIS_SET 1 << 2 |
| 157 | #define CFCLK_UPPER_MTST_DQS_EN_SET 1 << 1 |
| 158 | #define CFCLK_UPPER_MTEST_EN_SET 1 << 0 |
| 159 | |
| 160 | #define CFCLK_LOWER_MASK_CKE_SET1 1 << 9 |
| 161 | #define CFCLK_LOWER_MASK_CKE_SET0 1 << 8 |
| 162 | #define CFCLK_LOWER_SDCLK_SET 0Fh << 0 |
| 163 | |
| 164 | #define MC_CF_RDSYNC MSR_MC + 1Fh |
| 165 | |
| 166 | |
| 167 | /**/ |
| 168 | /* GLIU1 GLIU0 port2*/ |
| 169 | /**/ |
| 170 | #define GLIU1_GLD_MSR_CAP MSR_GLIU1 + 2000h |
| 171 | #define GLIU1_GLD_MSR_PM MSR_GLIU1 + 2004h |
| 172 | |
| 173 | #define GLIU1_GLD_MSR_COH MSR_GLIU1 + 80h |
| 174 | |
| 175 | |
| 176 | /**/ |
| 177 | /* CPU ; does not need routing instructions since we are executing there.*/ |
| 178 | /**/ |
| 179 | #define CPU_GLD_MSR_CAP 2000h |
| 180 | #define CPU_GLD_MSR_CONFIG 2001h |
| 181 | #define CPU_GLD_MSR_PM 2004h |
| 182 | |
| 183 | #define CPU_GLD_MSR_DIAG 2005h |
| 184 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 185 | #define DIAG_SEL1_SET 1 << 31 |
| 186 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 187 | #define DIAG_SET0_SET 1 << 15 |
| 188 | |
| 189 | #define CPU_PF_BTB_CONF 1100h |
| 190 | #define BTB_ENABLE_SET 1 << 0 |
| 191 | #define RETURN_STACK_ENABLE_SET 1 << 4 |
| 192 | #define CPU_PF_BTBRMA_BIST 110Ch |
| 193 | |
| 194 | #define CPU_XC_CONFIG 1210h |
| 195 | #define XC_CONFIG_SUSP_ON_HLT 1 << 0 |
| 196 | #define CPU_ID_CONFIG 1250h |
| 197 | #define ID_CONFIG_SERIAL_SET 1 << 0 |
| 198 | |
| 199 | #define CPU_AC_MSR 1301h |
| 200 | #define CPU_EX_BIST 1428h |
| 201 | |
| 202 | /*IM*/ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 203 | #define CPU_IM_CONFIG 0x1700 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 204 | #define IM_CONFIG_LOWER_ICD_SET 1 << 8 |
| 205 | #define IM_CONFIG_LOWER_QWT_SET 1 << 20 |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 206 | #define CPU_IC_INDEX 0x1710 |
| 207 | #define CPU_IC_DATA 0x1711 |
| 208 | #define CPU_IC_TAG 0x1712 |
| 209 | #define CPU_IC_TAG_I 0x1713 |
| 210 | #define CPU_ITB_INDEX 0x1720 |
| 211 | #define CPU_ITB_LRU 0x1721 |
| 212 | #define CPU_ITB_ENTRY 0x1722 |
| 213 | #define CPU_ITB_ENTRY_I 0x1723 |
| 214 | #define CPU_IM_BIST_TAG 0x1730 |
| 215 | #define CPU_IM_BIST_DATA 0x1731 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 216 | |
| 217 | |
| 218 | /* various CPU MSRs */ |
| 219 | #define CPU_DM_CONFIG0 0x1800 |
| 220 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
| 221 | #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) |
| 222 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
| 223 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
| 224 | /* configuration MSRs */ |
| 225 | #define CPU_RCONF_DEFAULT 0x1808 |
| 226 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 227 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 228 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 229 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 230 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 231 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 232 | |
| 233 | #define CPU_RCONF_BYPASS 0x180A |
| 234 | #define CPU_RCONF_A0_BF 0x180B |
| 235 | #define CPU_RCONF_C0_DF 0x180C |
| 236 | #define CPU_RCONF_E0_FF 0x180D |
| 237 | |
| 238 | #define CPU_RCONF_SMM 0x180E |
| 239 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 240 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 241 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 242 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 243 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 244 | |
| 245 | #define CPU_RCONF_DMM 0x180F |
| 246 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 247 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 248 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 249 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 250 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
| 251 | |
| 252 | #define CPU_RCONF0 0x1810 |
| 253 | #define CPU_RCONF1 0x1811 |
| 254 | #define CPU_RCONF2 0x1812 |
| 255 | #define CPU_RCONF3 0x1813 |
| 256 | #define CPU_RCONF4 0x1814 |
| 257 | #define CPU_RCONF5 0x1815 |
| 258 | #define CPU_RCONF6 0x1816 |
| 259 | #define CPU_RCONF7 0x1817 |
| 260 | #define CPU_CR1_MSR 0x1881 |
| 261 | #define CPU_CR2_MSR 0x1882 |
| 262 | #define CPU_CR3_MSR 0x1883 |
| 263 | #define CPU_CR4_MSR 0x1884 |
| 264 | #define CPU_DC_INDEX 0x1890 |
| 265 | #define CPU_DC_DATA 0x1891 |
| 266 | #define CPU_DC_TAG 0x1892 |
| 267 | #define CPU_DC_TAG_I 0x1893 |
| 268 | #define CPU_SNOOP 0x1894 |
| 269 | #define CPU_DTB_INDEX 0x1898 |
| 270 | #define CPU_DTB_LRU 0x1899 |
| 271 | #define CPU_DTB_ENTRY 0x189A |
| 272 | #define CPU_DTB_ENTRY_I 0x189B |
| 273 | #define CPU_L2TB_INDEX 0x189C |
| 274 | #define CPU_L2TB_LRU 0x189D |
| 275 | #define CPU_L2TB_ENTRY 0x189E |
| 276 | #define CPU_L2TB_ENTRY_I 0x189F |
| 277 | #define CPU_DM_BIST 0x18C0 |
| 278 | /* SMM*/ |
| 279 | #define CPU_AC_SMM_CTL 0x1301 |
| 280 | #define SMM_NMI_EN_SET (1<<0) |
| 281 | #define SMM_SUSP_EN_SET (1<<1) |
| 282 | #define NEST_SMI_EN_SET (1<<2) |
| 283 | #define SMM_INST_EN_SET (1<<3) |
| 284 | #define INTL_SMI_EN_SET (1<<4) |
| 285 | #define EXTL_SMI_EN_SET (1<<5) |
| 286 | |
| 287 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 288 | #define FPU_IE_SET (1<<0) |
| 289 | |
| 290 | #define CPU_FP_UROM_BIST 0x1A03 |
| 291 | |
| 292 | #define CPU_BC_CONF_0 0x1900 |
| 293 | #define TSC_SUSP_SET (1<<5) |
| 294 | #define SUSP_EN_SET (1<<1)2 |
| 295 | |
| 296 | /**/ |
| 297 | /* VG GLIU0 port4*/ |
| 298 | /**/ |
| 299 | |
| 300 | #define VG_GLD_MSR_CAP MSR_VG + 0x2000 |
| 301 | #define VG_GLD_MSR_CONFIG MSR_VG + 0x2001 |
| 302 | #define VG_GLD_MSR_PM MSR_VG + 0x2004 |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 303 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame^] | 304 | #define GP_GLD_MSR_CAP MSR_GP + 0x2000 |
| 305 | #define GP_GLD_MSR_CONFIG MSR_GP + 0x2001 |
| 306 | #define GP_GLD_MSR_PM MSR_GP + 0x2004 |
| 307 | |
| 308 | |
| 309 | |
| 310 | /**/ |
| 311 | /* DF GLIU0 port6*/ |
| 312 | /**/ |
| 313 | |
| 314 | #define DF_GLD_MSR_CAP MSR_DF + 0x2000 |
| 315 | #define DF_GLD_MSR_MASTER_CONF MSR_DF + 0x2001 |
| 316 | #define DF_LOWER_LCD_SHIFT 6 |
| 317 | #define DF_GLD_MSR_PM MSR_DF + 0x2004 |
| 318 | |
| 319 | |
| 320 | |
| 321 | /**/ |
| 322 | /* GeodeLink Control Processor GLIU1 port3*/ |
| 323 | /**/ |
| 324 | #define GLCP_GLD_MSR_CAP MSR_GLCP + 0x2000 |
| 325 | #define GLCP_GLD_MSR_CONF MSR_GLCP + 0x2001 |
| 326 | #define GLCP_GLD_MSR_PM MSR_GLCP + 0x2004 |
| 327 | |
| 328 | #define GLCP_DELAY_CONTROLS MSR_GLCP + 0x0F |
| 329 | |
| 330 | #define GLCP_SYS_RSTPLL MSR_GLCP +0x14 /* R/W*/ |
| 331 | #define RSTPLL_UPPER_MDIV_SHIFT 9 |
| 332 | #define RSTPLL_UPPER_VDIV_SHIFT 6 |
| 333 | #define RSTPLL_UPPER_FBDIV_SHIFT 0 |
| 334 | |
| 335 | #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 |
| 336 | #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)) |
| 337 | |
| 338 | #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 |
| 339 | #define RSTPPL_LOWER_BYPASS_SHIFT 15 |
| 340 | #define RSTPPL_LOWER_TST_SHIFT 11 |
| 341 | #define RSTPPL_LOWER_SDRMODE_SHIFT 10 |
| 342 | #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 |
| 343 | |
| 344 | #define RSTPPL_LOWER_LOCK_SET (1<<25) |
| 345 | #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) |
| 346 | #define RSTPPL_LOWER_BYPASS_SET (1<<15) |
| 347 | #define RSTPPL_LOWER_PD_SET (1<<14) |
| 348 | #define RSTPPL_LOWER_PLL_RESET_SET (1<<13) |
| 349 | #define RSTPPL_LOWER_SDRMODE_SET (1<<10) |
| 350 | #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) |
| 351 | #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) |
| 352 | #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) |
| 353 | |
| 354 | #define GLCP_DOTPLL MSR_GLCP + 0x15 /* R/W*/ |
| 355 | #define DOTPPL_LOWER_PD_SET (1<<14) |
| 356 | |
| 357 | |
| 358 | /**/ |
| 359 | /* GLIU1 port 4*/ |
| 360 | /**/ |
| 361 | #define GLPCI_GLD_MSR_CAP MSR_PCI + 0x2000 |
| 362 | #define GLPCI_GLD_MSR_CONFIG MSR_PCI + 0x2001 |
| 363 | #define GLPCI_GLD_MSR_PM MSR_PCI + 0x2004 |
| 364 | |
| 365 | #define GLPCI_CTRL MSR_PCI + 0x2010 |
| 366 | #define GLPCI_CTRL_UPPER_FTH_SHIFT 28 |
| 367 | #define GLPCI_CTRL_UPPER_RTH_SHIFT 24 |
| 368 | #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 |
| 369 | #define GLPCI_CTRL_UPPER_DTL_SHIFT 14 |
| 370 | #define GLPCI_CTRL_UPPER_WTO_SHIFT 11 |
| 371 | #define GLPCI_CTRL_UPPER_LAT_SHIFT 3 |
| 372 | #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 |
| 373 | #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 |
| 374 | #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 |
| 375 | #define GLPCI_CTRL_LOWER_ER_SET (1<<11) |
| 376 | #define GLPCI_CTRL_LOWER_LDE_SET (1<<9) |
| 377 | #define GLPCI_CTRL_LOWER_OWC_SET (1<<4) |
| 378 | #define GLPCI_CTRL_LOWER_IWC_SET (1<<3) |
| 379 | #define GLPCI_CTRL_LOWER_PCD_SET (1<<2) |
| 380 | #define GLPCI_CTRL_LOWER_ME_SET (1<<0) |
| 381 | |
| 382 | #define GLPCI_ARB MSR_PCI + 0x2011 |
| 383 | #define GLPCI_ARB_UPPER_BM1_SET (1<<17) |
| 384 | #define GLPCI_ARB_UPPER_BM0_SET (1<<16) |
| 385 | #define GLPCI_ARB_UPPER_CPRE_SET (1<<15) |
| 386 | #define GLPCI_ARB_UPPER_PRE2_SET (1<<10) |
| 387 | #define GLPCI_ARB_UPPER_PRE1_SET (1<<9) |
| 388 | #define GLPCI_ARB_UPPER_PRE0_SET (1<<8) |
| 389 | #define GLPCI_ARB_UPPER_CRME_SET (1<<7) |
| 390 | #define GLPCI_ARB_UPPER_RME2_SET (1<<2) |
| 391 | #define GLPCI_ARB_UPPER_RME1_SET (1<<1) |
| 392 | #define GLPCI_ARB_UPPER_RME0_SET (1<<0) |
| 393 | #define GLPCI_ARB_LOWER_PRCM_SHIFT 24 |
| 394 | #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 |
| 395 | #define GLPCI_ARB_LOWER_RMT_SHIFT 6 |
| 396 | #define GLPCI_ARB_LOWER_IIE_SET (1<<8) |
| 397 | #define GLPCI_ARB_LOWER_PARK_SET (1<<0) |
| 398 | |
| 399 | #define GLPCI_REN MSR_PCI + 0x2014 |
| 400 | #define GLPCI_A0_BF MSR_PCI + 0x2015 |
| 401 | #define GLPCI_C0_DF MSR_PCI + 0x2016 |
| 402 | #define GLPCI_E0_FF MSR_PCI + 0x2017 |
| 403 | #define GLPCI_RC0 MSR_PCI + 0x2018 |
| 404 | #define GLPCI_RC1 MSR_PCI + 0x2019 |
| 405 | #define GLPCI_RC2 MSR_PCI + 0x201A |
| 406 | #define GLPCI_RC3 MSR_PCI + 0x201B |
| 407 | #define GLPCI_RC4 MSR_PCI + 0x201C |
| 408 | #define GLPCI_RC_UPPER_TOP_SHIFT 12 |
| 409 | #define GLPCI_RC_LOWER_BASE_SHIFT 12 |
| 410 | #define GLPCI_RC_LOWER_EN_SET (1<<8) |
| 411 | #define GLPCI_RC_LOWER_PF_SET (1<<5) |
| 412 | #define GLPCI_RC_LOWER_WC_SET (1<<4) |
| 413 | #define GLPCI_RC_LOWER_WP_SET (1<<2) |
| 414 | #define GLPCI_RC_LOWER_CD_SET (1<<0) |
| 415 | #define GLPCI_ExtMSR MSR_PCI + 0x201E |
| 416 | #define GLPCI_SPARE MSR_PCI + 0x201F |
| 417 | #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) |
| 418 | #define GLPCI_SPARE_LOWER_PPD_SET (1<<5) |
| 419 | #define GLPCI_SPARE_LOWER_PPC_SET (1<<4) |
| 420 | #define GLPCI_SPARE_LOWER_MPC_SET (1<<3) |
| 421 | #define GLPCI_SPARE_LOWER_MME_SET (1<<2) |
| 422 | #define GLPCI_SPARE_LOWER_NSE_SET (1<<1) |
| 423 | #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) |
| 424 | |
| 425 | |
| 426 | /**/ |
| 427 | /* FooGlue GLIU1 port 5*/ |
| 428 | /**/ |
| 429 | #define FG_GLD_MSR_CAP MSR_FG + 0x2000 |
| 430 | #define FG_GLD_MSR_PM MSR_FG + 0x2004 |
| 431 | |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 432 | #endif /* CPU_AMD_GX2DEF_H */ |