Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 1 | #ifndef CPU_AMD_GX2DEF_H |
| 2 | #define CPU_AMD_GX2DEF_H |
| 3 | |
| 4 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ |
| 5 | #define GLCP_CLK_DIS_DELAY 0x4c000008 |
| 6 | #define GLCP_PMCLKDISABLE 0x4c000009 |
| 7 | #define GLCP_DELAY_CONTROLS 0x4c00000f |
| 8 | #define GLCP_SYS_RSTPLL 0x4c000014 |
| 9 | #define GLCP_DOTPLL 0x4c000015 |
Ronald G. Minnich | c4ca49b | 2006-03-20 17:31:02 +0000 | [diff] [blame] | 10 | #define GLCP_CHIP_REVID 0x4c000017 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame^] | 11 | /* MSR routing as follows*/ |
| 12 | /* MSB = 1 means not for CPU*/ |
| 13 | /* next 3 bits 1st port*/ |
| 14 | /* next3 bits next port if through an GLIU*/ |
| 15 | /* etc...*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 16 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame^] | 17 | /*Redcloud as follows.*/ |
| 18 | /* GLIU0*/ |
| 19 | /* port0 - GLIU0*/ |
| 20 | /* port1 - MC*/ |
| 21 | /* port2 - GLIU1*/ |
| 22 | /* port3 - CPU*/ |
| 23 | /* port4 - VG*/ |
| 24 | /* port5 - GP*/ |
| 25 | /* port6 - DF*/ |
| 26 | |
| 27 | /* GLIU1*/ |
| 28 | /* port1 - GLIU0*/ |
| 29 | /* port3 - GLCP*/ |
| 30 | /* port4 - PCI*/ |
| 31 | /* port5 - FG*/ |
| 32 | |
| 33 | |
| 34 | #define GL0_GLIU0 0 |
| 35 | #define GL0_MC 1 |
| 36 | #define GL0_GLIU1 2 |
| 37 | #define GL0_CPU 3 |
| 38 | #define GL0_VG 4 |
| 39 | #define GL0_GP 5 |
| 40 | #define GL0_DF 6 |
| 41 | |
| 42 | #define GL1_GLIU0 1 |
| 43 | #define GL1_GLCP 3 |
| 44 | #define GL1_PCI 4 |
| 45 | #define GL1_FG 5 |
| 46 | |
| 47 | |
| 48 | #define MSR_GLIU0 (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */ |
| 49 | #define MSR_MC GL0_MC << 29 |
| 50 | #define MSR_GLIU1 GL0_GLIU1 << 29 |
| 51 | #define MSR_CPU GL0_CPU << 29 /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/ |
| 52 | #define MSR_VG GL0_VG << 29 |
| 53 | #define MSR_GP GL0_GP << 29 |
| 54 | #define MSR_DF GL0_DF << 29 |
| 55 | |
| 56 | #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 |
| 57 | #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 |
| 58 | #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 |
| 59 | |
| 60 | /* South Bridge*/ |
| 61 | #define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/ |
| 62 | #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ |
| 63 | |
| 64 | |
| 65 | /**/ |
| 66 | /*GeodeLink Interface Unit 0 (GLIU0) port0*/ |
| 67 | /**/ |
| 68 | |
| 69 | #define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 2000h |
| 70 | #define GLIU0_GLD_MSR_PM MSR_GLIU0 + 2004h |
| 71 | |
| 72 | #define GLIU0_DESC_BASE MSR_GLIU0 + 20h |
| 73 | #define GLIU0_CAP MSR_GLIU0 + 86h |
| 74 | #define GLIU0_GLD_MSR_COH MSR_GLIU0 + 80h |
| 75 | |
| 76 | |
| 77 | /**/ |
| 78 | /* Memory Controller GLIU0 port 1*/ |
| 79 | /**/ |
| 80 | #define MC_GLD_MSR_CAP MSR_MC + 2000h |
| 81 | #define MC_GLD_MSR_PM MSR_MC + 2004h |
| 82 | |
| 83 | #define MC_CF07_DATA MSR_MC + 18h |
| 84 | |
| 85 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 86 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 87 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 88 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 89 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 90 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 91 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 92 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 93 | |
| 94 | #define CF07_LOWER_REF_INT_SHIFT 8 |
| 95 | #define CF07_LOWER_LOAD_MODE_DDR_SET 01 << 28 |
| 96 | #define CF07_LOWER_LOAD_MODE_DLL_RESET 01 << 27 |
| 97 | #define CF07_LOWER_EMR_QFC_SET 01 << 26 |
| 98 | #define CF07_LOWER_EMR_DRV_SET 01 << 25 |
| 99 | #define CF07_LOWER_REF_TEST_SET 1 << 3 |
| 100 | #define CF07_LOWER_PROG_DRAM_SET 1 << 0 |
| 101 | |
| 102 | |
| 103 | #define MC_CF8F_DATA MSR_MC + 19h |
| 104 | |
| 105 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 106 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 107 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 108 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 109 | #define CF8F_UPPER_REORDER_DIS_SET 1 << 8 |
| 110 | #define CF8F_UPPER_REG_DIMM_SHIFT 4 |
| 111 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
| 112 | #define CF8F_LOWER_REF2ACT_SHIFT 24 |
| 113 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 114 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 115 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 116 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
| 117 | #define CF8F_UPPER_32BIT_SET 1 << 5 |
| 118 | #define CF8F_UPPER_HOI_LOI_SET 1 << 1 |
| 119 | |
| 120 | #define MC_CF1017_DATA MSR_MC + 1Ah |
| 121 | |
| 122 | #define CF1017_LOWER_PM1_UP_DLY_SET 1 << 8 |
| 123 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
| 124 | |
| 125 | #define MC_CFCLK_DBUG MSR_MC + 1Dh |
| 126 | |
| 127 | #define CFCLK_UPPER_MTST_B2B_DIS_SET 1 << 2 |
| 128 | #define CFCLK_UPPER_MTST_DQS_EN_SET 1 << 1 |
| 129 | #define CFCLK_UPPER_MTEST_EN_SET 1 << 0 |
| 130 | |
| 131 | #define CFCLK_LOWER_MASK_CKE_SET1 1 << 9 |
| 132 | #define CFCLK_LOWER_MASK_CKE_SET0 1 << 8 |
| 133 | #define CFCLK_LOWER_SDCLK_SET 0Fh << 0 |
| 134 | |
| 135 | #define MC_CF_RDSYNC MSR_MC + 1Fh |
| 136 | |
| 137 | |
| 138 | /**/ |
| 139 | /* GLIU1 GLIU0 port2*/ |
| 140 | /**/ |
| 141 | #define GLIU1_GLD_MSR_CAP MSR_GLIU1 + 2000h |
| 142 | #define GLIU1_GLD_MSR_PM MSR_GLIU1 + 2004h |
| 143 | |
| 144 | #define GLIU1_GLD_MSR_COH MSR_GLIU1 + 80h |
| 145 | |
| 146 | |
| 147 | /**/ |
| 148 | /* CPU ; does not need routing instructions since we are executing there.*/ |
| 149 | /**/ |
| 150 | #define CPU_GLD_MSR_CAP 2000h |
| 151 | #define CPU_GLD_MSR_CONFIG 2001h |
| 152 | #define CPU_GLD_MSR_PM 2004h |
| 153 | |
| 154 | #define CPU_GLD_MSR_DIAG 2005h |
| 155 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 156 | #define DIAG_SEL1_SET 1 << 31 |
| 157 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 158 | #define DIAG_SET0_SET 1 << 15 |
| 159 | |
| 160 | #define CPU_PF_BTB_CONF 1100h |
| 161 | #define BTB_ENABLE_SET 1 << 0 |
| 162 | #define RETURN_STACK_ENABLE_SET 1 << 4 |
| 163 | #define CPU_PF_BTBRMA_BIST 110Ch |
| 164 | |
| 165 | #define CPU_XC_CONFIG 1210h |
| 166 | #define XC_CONFIG_SUSP_ON_HLT 1 << 0 |
| 167 | #define CPU_ID_CONFIG 1250h |
| 168 | #define ID_CONFIG_SERIAL_SET 1 << 0 |
| 169 | |
| 170 | #define CPU_AC_MSR 1301h |
| 171 | #define CPU_EX_BIST 1428h |
| 172 | |
| 173 | /*IM*/ |
| 174 | #define CPU_IM_CONFIG 1700h |
| 175 | #define IM_CONFIG_LOWER_ICD_SET 1 << 8 |
| 176 | #define IM_CONFIG_LOWER_QWT_SET 1 << 20 |
| 177 | #define CPU_IC_INDEX 1710h |
| 178 | #define CPU_IC_DATA 1711h |
| 179 | #define CPU_IC_TAG 1712h |
| 180 | #define CPU_IC_TAG_I 1713h |
| 181 | #define CPU_ITB_INDEX 1720h |
| 182 | #define CPU_ITB_LRU 1721h |
| 183 | #define CPU_ITB_ENTRY 1722h |
| 184 | #define CPU_ITB_ENTRY_I 1723h |
| 185 | #define CPU_IM_BIST_TAG 1730h |
| 186 | #define CPU_IM_BIST_DATA 1731h |
| 187 | |
| 188 | |
| 189 | /* various CPU MSRs */ |
| 190 | #define CPU_DM_CONFIG0 0x1800 |
| 191 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
| 192 | #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) |
| 193 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
| 194 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
| 195 | /* configuration MSRs */ |
| 196 | #define CPU_RCONF_DEFAULT 0x1808 |
| 197 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 198 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 199 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 200 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 201 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 202 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 203 | |
| 204 | #define CPU_RCONF_BYPASS 0x180A |
| 205 | #define CPU_RCONF_A0_BF 0x180B |
| 206 | #define CPU_RCONF_C0_DF 0x180C |
| 207 | #define CPU_RCONF_E0_FF 0x180D |
| 208 | |
| 209 | #define CPU_RCONF_SMM 0x180E |
| 210 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 211 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 212 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 213 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 214 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 215 | |
| 216 | #define CPU_RCONF_DMM 0x180F |
| 217 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 218 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 219 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 220 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 221 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
| 222 | |
| 223 | #define CPU_RCONF0 0x1810 |
| 224 | #define CPU_RCONF1 0x1811 |
| 225 | #define CPU_RCONF2 0x1812 |
| 226 | #define CPU_RCONF3 0x1813 |
| 227 | #define CPU_RCONF4 0x1814 |
| 228 | #define CPU_RCONF5 0x1815 |
| 229 | #define CPU_RCONF6 0x1816 |
| 230 | #define CPU_RCONF7 0x1817 |
| 231 | #define CPU_CR1_MSR 0x1881 |
| 232 | #define CPU_CR2_MSR 0x1882 |
| 233 | #define CPU_CR3_MSR 0x1883 |
| 234 | #define CPU_CR4_MSR 0x1884 |
| 235 | #define CPU_DC_INDEX 0x1890 |
| 236 | #define CPU_DC_DATA 0x1891 |
| 237 | #define CPU_DC_TAG 0x1892 |
| 238 | #define CPU_DC_TAG_I 0x1893 |
| 239 | #define CPU_SNOOP 0x1894 |
| 240 | #define CPU_DTB_INDEX 0x1898 |
| 241 | #define CPU_DTB_LRU 0x1899 |
| 242 | #define CPU_DTB_ENTRY 0x189A |
| 243 | #define CPU_DTB_ENTRY_I 0x189B |
| 244 | #define CPU_L2TB_INDEX 0x189C |
| 245 | #define CPU_L2TB_LRU 0x189D |
| 246 | #define CPU_L2TB_ENTRY 0x189E |
| 247 | #define CPU_L2TB_ENTRY_I 0x189F |
| 248 | #define CPU_DM_BIST 0x18C0 |
| 249 | /* SMM*/ |
| 250 | #define CPU_AC_SMM_CTL 0x1301 |
| 251 | #define SMM_NMI_EN_SET (1<<0) |
| 252 | #define SMM_SUSP_EN_SET (1<<1) |
| 253 | #define NEST_SMI_EN_SET (1<<2) |
| 254 | #define SMM_INST_EN_SET (1<<3) |
| 255 | #define INTL_SMI_EN_SET (1<<4) |
| 256 | #define EXTL_SMI_EN_SET (1<<5) |
| 257 | |
| 258 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 259 | #define FPU_IE_SET (1<<0) |
| 260 | |
| 261 | #define CPU_FP_UROM_BIST 0x1A03 |
| 262 | |
| 263 | #define CPU_BC_CONF_0 0x1900 |
| 264 | #define TSC_SUSP_SET (1<<5) |
| 265 | #define SUSP_EN_SET (1<<1)2 |
| 266 | |
| 267 | /**/ |
| 268 | /* VG GLIU0 port4*/ |
| 269 | /**/ |
| 270 | |
| 271 | #define VG_GLD_MSR_CAP MSR_VG + 0x2000 |
| 272 | #define VG_GLD_MSR_CONFIG MSR_VG + 0x2001 |
| 273 | #define VG_GLD_MSR_PM MSR_VG + 0x2004 |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 274 | |
| 275 | /* Upper 32 bits */ |
| 276 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 277 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 278 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
| 279 | |
| 280 | /* Lower 32 bits */ |
| 281 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 282 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 283 | |
| 284 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 285 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 286 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 287 | #define GLCP_SYS_RSTPLL_PD 14 |
| 288 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 289 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 290 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 291 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 292 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
| 293 | |
| 294 | #endif /* CPU_AMD_GX2DEF_H */ |