Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 1 | #ifndef CPU_AMD_GX2DEF_H |
| 2 | #define CPU_AMD_GX2DEF_H |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 3 | #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ |
| 4 | #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ |
| 5 | #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ |
| 6 | #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 7 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 8 | #define CPU_REV_1_0 0x011 |
| 9 | #define CPU_REV_1_1 0x012 |
| 10 | #define CPU_REV_1_2 0x013 |
| 11 | #define CPU_REV_1_3 0x014 |
| 12 | #define CPU_REV_2_0 0x020 |
| 13 | #define CPU_REV_2_1 0x021 |
| 14 | #define CPU_REV_2_2 0x022 |
| 15 | #define CPU_REV_3_0 0x030 |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 16 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ |
| 17 | #define GLCP_CLK_DIS_DELAY 0x4c000008 |
| 18 | #define GLCP_PMCLKDISABLE 0x4c000009 |
Li-Ta Lo | af9484a | 2006-03-20 21:18:53 +0000 | [diff] [blame] | 19 | #define GLCP_CHIP_REVID 0x4c000017 |
| 20 | |
| 21 | /* GLCP_SYS_RSTPLL, Upper 32 bits */ |
| 22 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 23 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 24 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
| 25 | |
| 26 | /* GLCP_SYS_RSTPLL, Lower 32 bits */ |
| 27 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 28 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 29 | |
| 30 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 31 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 32 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 33 | #define GLCP_SYS_RSTPLL_PD 14 |
| 34 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 35 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 36 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 37 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 38 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
| 39 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 40 | /* MSR routing as follows*/ |
| 41 | /* MSB = 1 means not for CPU*/ |
| 42 | /* next 3 bits 1st port*/ |
| 43 | /* next3 bits next port if through an GLIU*/ |
| 44 | /* etc...*/ |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 45 | |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 46 | /*Redcloud as follows.*/ |
| 47 | /* GLIU0*/ |
| 48 | /* port0 - GLIU0*/ |
| 49 | /* port1 - MC*/ |
| 50 | /* port2 - GLIU1*/ |
| 51 | /* port3 - CPU*/ |
| 52 | /* port4 - VG*/ |
| 53 | /* port5 - GP*/ |
| 54 | /* port6 - DF*/ |
| 55 | |
| 56 | /* GLIU1*/ |
| 57 | /* port1 - GLIU0*/ |
| 58 | /* port3 - GLCP*/ |
| 59 | /* port4 - PCI*/ |
| 60 | /* port5 - FG*/ |
| 61 | |
| 62 | |
| 63 | #define GL0_GLIU0 0 |
| 64 | #define GL0_MC 1 |
| 65 | #define GL0_GLIU1 2 |
| 66 | #define GL0_CPU 3 |
| 67 | #define GL0_VG 4 |
| 68 | #define GL0_GP 5 |
| 69 | #define GL0_DF 6 |
| 70 | |
| 71 | #define GL1_GLIU0 1 |
| 72 | #define GL1_GLCP 3 |
| 73 | #define GL1_PCI 4 |
| 74 | #define GL1_FG 5 |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame^] | 75 | #define GL1_VIP 5 |
| 76 | #define GL1_AES 6 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 77 | |
Ronald G. Minnich | 44f72eb | 2006-04-06 20:45:10 +0000 | [diff] [blame] | 78 | #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* To get on GeodeLink one bit has to be set */ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 79 | #define MSR_MC (GL0_MC << 29) |
| 80 | #define MSR_GLIU1 (GL0_GLIU1 << 29) |
| 81 | #define MSR_CPU (GL0_CPU << 29) /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/ |
| 82 | #define MSR_VG (GL0_VG << 29) |
| 83 | #define MSR_GP (GL0_GP << 29) |
| 84 | #define MSR_DF (GL0_DF << 29) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 85 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 86 | #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 87 | #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 |
| 88 | #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame^] | 89 | #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) |
| 90 | #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 91 | /* South Bridge*/ |
| 92 | #define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/ |
| 93 | #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ |
| 94 | |
| 95 | |
| 96 | /**/ |
| 97 | /*GeodeLink Interface Unit 0 (GLIU0) port0*/ |
| 98 | /**/ |
| 99 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 100 | #define GLIU0_GLD_MSR_CAP MSR_GLIU0 + 0x2000 |
| 101 | #define GLIU0_GLD_MSR_PM MSR_GLIU0 + 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 102 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 103 | #define GLIU0_DESC_BASE MSR_GLIU0 + 0x20 |
| 104 | #define GLIU0_CAP MSR_GLIU0 + 0x86 |
| 105 | #define GLIU0_GLD_MSR_COH MSR_GLIU0 + 0x80 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 106 | |
| 107 | |
| 108 | /**/ |
| 109 | /* Memory Controller GLIU0 port 1*/ |
| 110 | /**/ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 111 | #define MC_GLD_MSR_CAP MSR_MC + 0x2000 |
| 112 | #define MC_GLD_MSR_PM MSR_MC + 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 113 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 114 | #define MC_CF07_DATA MSR_MC + 0x18 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 115 | |
| 116 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 117 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 118 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 119 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 120 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 121 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 122 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 123 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 124 | |
| 125 | #define CF07_LOWER_REF_INT_SHIFT 8 |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 126 | #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) |
| 127 | #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) |
| 128 | #define CF07_LOWER_EMR_QFC_SET (1 << 26) |
| 129 | #define CF07_LOWER_EMR_DRV_SET (1 << 25) |
| 130 | #define CF07_LOWER_REF_TEST_SET (1 << 3) |
| 131 | #define CF07_LOWER_PROG_DRAM_SET (1 << 0) |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 132 | |
| 133 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 134 | #define MC_CF8F_DATA MSR_MC + 0x19 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 135 | |
| 136 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 137 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 138 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 139 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 140 | #define CF8F_UPPER_REORDER_DIS_SET 1 << 8 |
| 141 | #define CF8F_UPPER_REG_DIMM_SHIFT 4 |
| 142 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
| 143 | #define CF8F_LOWER_REF2ACT_SHIFT 24 |
| 144 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 145 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 146 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 147 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
| 148 | #define CF8F_UPPER_32BIT_SET 1 << 5 |
| 149 | #define CF8F_UPPER_HOI_LOI_SET 1 << 1 |
| 150 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 151 | #define MC_CF1017_DATA MSR_MC + 0x1A |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 152 | |
| 153 | #define CF1017_LOWER_PM1_UP_DLY_SET 1 << 8 |
| 154 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
| 155 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 156 | #define MC_CFCLK_DBUG MSR_MC + 0x1D |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 157 | |
| 158 | #define CFCLK_UPPER_MTST_B2B_DIS_SET 1 << 2 |
| 159 | #define CFCLK_UPPER_MTST_DQS_EN_SET 1 << 1 |
| 160 | #define CFCLK_UPPER_MTEST_EN_SET 1 << 0 |
| 161 | |
| 162 | #define CFCLK_LOWER_MASK_CKE_SET1 1 << 9 |
| 163 | #define CFCLK_LOWER_MASK_CKE_SET0 1 << 8 |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 164 | #define CFCLK_LOWER_SDCLK_SET 0x0F << 0 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 165 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 166 | #define MC_CF_RDSYNC MSR_MC + 0x1F |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 167 | |
| 168 | |
| 169 | /**/ |
| 170 | /* GLIU1 GLIU0 port2*/ |
| 171 | /**/ |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 172 | #define GLIU1_GLD_MSR_CAP MSR_GLIU1 + 0x2000 |
| 173 | #define GLIU1_GLD_MSR_PM MSR_GLIU1 + 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 174 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 175 | #define GLIU1_GLD_MSR_COH MSR_GLIU1 + 0x80 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 176 | |
| 177 | |
| 178 | /**/ |
| 179 | /* CPU ; does not need routing instructions since we are executing there.*/ |
| 180 | /**/ |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 181 | #define CPU_GLD_MSR_CAP 0x2000 |
| 182 | #define CPU_GLD_MSR_CONFIG 0x2001 |
| 183 | #define CPU_GLD_MSR_PM 0x2004 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 184 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 185 | #define CPU_GLD_MSR_DIAG 0x2005 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 186 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 187 | #define DIAG_SEL1_SET 1 << 31 |
| 188 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 189 | #define DIAG_SET0_SET 1 << 15 |
| 190 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 191 | #define CPU_PF_BTB_CONF 0x1100 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 192 | #define BTB_ENABLE_SET 1 << 0 |
| 193 | #define RETURN_STACK_ENABLE_SET 1 << 4 |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 194 | #define CPU_PF_BTBRMA_BIST 0x110C |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 195 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 196 | #define CPU_XC_CONFIG 0x1210 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 197 | #define XC_CONFIG_SUSP_ON_HLT 1 << 0 |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 198 | #define CPU_ID_CONFIG 0x1250 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 199 | #define ID_CONFIG_SERIAL_SET 1 << 0 |
| 200 | |
Ronald G. Minnich | f01f154 | 2006-04-06 21:45:24 +0000 | [diff] [blame] | 201 | #define CPU_AC_MSR 0x1301 |
| 202 | #define CPU_EX_BIST 0x1428 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 203 | |
| 204 | /*IM*/ |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 205 | #define CPU_IM_CONFIG 0x1700 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 206 | #define IM_CONFIG_LOWER_ICD_SET 1 << 8 |
| 207 | #define IM_CONFIG_LOWER_QWT_SET 1 << 20 |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 208 | #define CPU_IC_INDEX 0x1710 |
| 209 | #define CPU_IC_DATA 0x1711 |
| 210 | #define CPU_IC_TAG 0x1712 |
| 211 | #define CPU_IC_TAG_I 0x1713 |
| 212 | #define CPU_ITB_INDEX 0x1720 |
| 213 | #define CPU_ITB_LRU 0x1721 |
| 214 | #define CPU_ITB_ENTRY 0x1722 |
| 215 | #define CPU_ITB_ENTRY_I 0x1723 |
| 216 | #define CPU_IM_BIST_TAG 0x1730 |
| 217 | #define CPU_IM_BIST_DATA 0x1731 |
Ronald G. Minnich | db44be9 | 2006-03-20 20:49:34 +0000 | [diff] [blame] | 218 | |
| 219 | |
| 220 | /* various CPU MSRs */ |
| 221 | #define CPU_DM_CONFIG0 0x1800 |
| 222 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
| 223 | #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) |
| 224 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
| 225 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
| 226 | /* configuration MSRs */ |
| 227 | #define CPU_RCONF_DEFAULT 0x1808 |
| 228 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 229 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 230 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 231 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 232 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 233 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 234 | |
| 235 | #define CPU_RCONF_BYPASS 0x180A |
| 236 | #define CPU_RCONF_A0_BF 0x180B |
| 237 | #define CPU_RCONF_C0_DF 0x180C |
| 238 | #define CPU_RCONF_E0_FF 0x180D |
| 239 | |
| 240 | #define CPU_RCONF_SMM 0x180E |
| 241 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 242 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 243 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 244 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 245 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 246 | |
| 247 | #define CPU_RCONF_DMM 0x180F |
| 248 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 249 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 250 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 251 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 252 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
| 253 | |
| 254 | #define CPU_RCONF0 0x1810 |
| 255 | #define CPU_RCONF1 0x1811 |
| 256 | #define CPU_RCONF2 0x1812 |
| 257 | #define CPU_RCONF3 0x1813 |
| 258 | #define CPU_RCONF4 0x1814 |
| 259 | #define CPU_RCONF5 0x1815 |
| 260 | #define CPU_RCONF6 0x1816 |
| 261 | #define CPU_RCONF7 0x1817 |
| 262 | #define CPU_CR1_MSR 0x1881 |
| 263 | #define CPU_CR2_MSR 0x1882 |
| 264 | #define CPU_CR3_MSR 0x1883 |
| 265 | #define CPU_CR4_MSR 0x1884 |
| 266 | #define CPU_DC_INDEX 0x1890 |
| 267 | #define CPU_DC_DATA 0x1891 |
| 268 | #define CPU_DC_TAG 0x1892 |
| 269 | #define CPU_DC_TAG_I 0x1893 |
| 270 | #define CPU_SNOOP 0x1894 |
| 271 | #define CPU_DTB_INDEX 0x1898 |
| 272 | #define CPU_DTB_LRU 0x1899 |
| 273 | #define CPU_DTB_ENTRY 0x189A |
| 274 | #define CPU_DTB_ENTRY_I 0x189B |
| 275 | #define CPU_L2TB_INDEX 0x189C |
| 276 | #define CPU_L2TB_LRU 0x189D |
| 277 | #define CPU_L2TB_ENTRY 0x189E |
| 278 | #define CPU_L2TB_ENTRY_I 0x189F |
| 279 | #define CPU_DM_BIST 0x18C0 |
| 280 | /* SMM*/ |
| 281 | #define CPU_AC_SMM_CTL 0x1301 |
| 282 | #define SMM_NMI_EN_SET (1<<0) |
| 283 | #define SMM_SUSP_EN_SET (1<<1) |
| 284 | #define NEST_SMI_EN_SET (1<<2) |
| 285 | #define SMM_INST_EN_SET (1<<3) |
| 286 | #define INTL_SMI_EN_SET (1<<4) |
| 287 | #define EXTL_SMI_EN_SET (1<<5) |
| 288 | |
| 289 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 290 | #define FPU_IE_SET (1<<0) |
| 291 | |
| 292 | #define CPU_FP_UROM_BIST 0x1A03 |
| 293 | |
| 294 | #define CPU_BC_CONF_0 0x1900 |
| 295 | #define TSC_SUSP_SET (1<<5) |
| 296 | #define SUSP_EN_SET (1<<1)2 |
| 297 | |
| 298 | /**/ |
| 299 | /* VG GLIU0 port4*/ |
| 300 | /**/ |
| 301 | |
| 302 | #define VG_GLD_MSR_CAP MSR_VG + 0x2000 |
| 303 | #define VG_GLD_MSR_CONFIG MSR_VG + 0x2001 |
| 304 | #define VG_GLD_MSR_PM MSR_VG + 0x2004 |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 305 | |
Ronald G. Minnich | 316ea53 | 2006-03-20 22:20:09 +0000 | [diff] [blame] | 306 | #define GP_GLD_MSR_CAP MSR_GP + 0x2000 |
| 307 | #define GP_GLD_MSR_CONFIG MSR_GP + 0x2001 |
| 308 | #define GP_GLD_MSR_PM MSR_GP + 0x2004 |
| 309 | |
| 310 | |
| 311 | |
| 312 | /**/ |
| 313 | /* DF GLIU0 port6*/ |
| 314 | /**/ |
| 315 | |
| 316 | #define DF_GLD_MSR_CAP MSR_DF + 0x2000 |
| 317 | #define DF_GLD_MSR_MASTER_CONF MSR_DF + 0x2001 |
| 318 | #define DF_LOWER_LCD_SHIFT 6 |
| 319 | #define DF_GLD_MSR_PM MSR_DF + 0x2004 |
| 320 | |
| 321 | |
| 322 | |
| 323 | /**/ |
| 324 | /* GeodeLink Control Processor GLIU1 port3*/ |
| 325 | /**/ |
| 326 | #define GLCP_GLD_MSR_CAP MSR_GLCP + 0x2000 |
| 327 | #define GLCP_GLD_MSR_CONF MSR_GLCP + 0x2001 |
| 328 | #define GLCP_GLD_MSR_PM MSR_GLCP + 0x2004 |
| 329 | |
| 330 | #define GLCP_DELAY_CONTROLS MSR_GLCP + 0x0F |
| 331 | |
| 332 | #define GLCP_SYS_RSTPLL MSR_GLCP +0x14 /* R/W*/ |
| 333 | #define RSTPLL_UPPER_MDIV_SHIFT 9 |
| 334 | #define RSTPLL_UPPER_VDIV_SHIFT 6 |
| 335 | #define RSTPLL_UPPER_FBDIV_SHIFT 0 |
| 336 | |
| 337 | #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 |
| 338 | #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)) |
| 339 | |
| 340 | #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 |
| 341 | #define RSTPPL_LOWER_BYPASS_SHIFT 15 |
| 342 | #define RSTPPL_LOWER_TST_SHIFT 11 |
| 343 | #define RSTPPL_LOWER_SDRMODE_SHIFT 10 |
| 344 | #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 |
| 345 | |
| 346 | #define RSTPPL_LOWER_LOCK_SET (1<<25) |
| 347 | #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) |
| 348 | #define RSTPPL_LOWER_BYPASS_SET (1<<15) |
| 349 | #define RSTPPL_LOWER_PD_SET (1<<14) |
| 350 | #define RSTPPL_LOWER_PLL_RESET_SET (1<<13) |
| 351 | #define RSTPPL_LOWER_SDRMODE_SET (1<<10) |
| 352 | #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) |
| 353 | #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) |
| 354 | #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) |
| 355 | |
| 356 | #define GLCP_DOTPLL MSR_GLCP + 0x15 /* R/W*/ |
| 357 | #define DOTPPL_LOWER_PD_SET (1<<14) |
| 358 | |
| 359 | |
| 360 | /**/ |
| 361 | /* GLIU1 port 4*/ |
| 362 | /**/ |
| 363 | #define GLPCI_GLD_MSR_CAP MSR_PCI + 0x2000 |
| 364 | #define GLPCI_GLD_MSR_CONFIG MSR_PCI + 0x2001 |
| 365 | #define GLPCI_GLD_MSR_PM MSR_PCI + 0x2004 |
| 366 | |
| 367 | #define GLPCI_CTRL MSR_PCI + 0x2010 |
| 368 | #define GLPCI_CTRL_UPPER_FTH_SHIFT 28 |
| 369 | #define GLPCI_CTRL_UPPER_RTH_SHIFT 24 |
| 370 | #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 |
| 371 | #define GLPCI_CTRL_UPPER_DTL_SHIFT 14 |
| 372 | #define GLPCI_CTRL_UPPER_WTO_SHIFT 11 |
| 373 | #define GLPCI_CTRL_UPPER_LAT_SHIFT 3 |
| 374 | #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 |
| 375 | #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 |
| 376 | #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 |
| 377 | #define GLPCI_CTRL_LOWER_ER_SET (1<<11) |
| 378 | #define GLPCI_CTRL_LOWER_LDE_SET (1<<9) |
| 379 | #define GLPCI_CTRL_LOWER_OWC_SET (1<<4) |
| 380 | #define GLPCI_CTRL_LOWER_IWC_SET (1<<3) |
| 381 | #define GLPCI_CTRL_LOWER_PCD_SET (1<<2) |
| 382 | #define GLPCI_CTRL_LOWER_ME_SET (1<<0) |
| 383 | |
| 384 | #define GLPCI_ARB MSR_PCI + 0x2011 |
| 385 | #define GLPCI_ARB_UPPER_BM1_SET (1<<17) |
| 386 | #define GLPCI_ARB_UPPER_BM0_SET (1<<16) |
| 387 | #define GLPCI_ARB_UPPER_CPRE_SET (1<<15) |
| 388 | #define GLPCI_ARB_UPPER_PRE2_SET (1<<10) |
| 389 | #define GLPCI_ARB_UPPER_PRE1_SET (1<<9) |
| 390 | #define GLPCI_ARB_UPPER_PRE0_SET (1<<8) |
| 391 | #define GLPCI_ARB_UPPER_CRME_SET (1<<7) |
| 392 | #define GLPCI_ARB_UPPER_RME2_SET (1<<2) |
| 393 | #define GLPCI_ARB_UPPER_RME1_SET (1<<1) |
| 394 | #define GLPCI_ARB_UPPER_RME0_SET (1<<0) |
| 395 | #define GLPCI_ARB_LOWER_PRCM_SHIFT 24 |
| 396 | #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 |
| 397 | #define GLPCI_ARB_LOWER_RMT_SHIFT 6 |
| 398 | #define GLPCI_ARB_LOWER_IIE_SET (1<<8) |
| 399 | #define GLPCI_ARB_LOWER_PARK_SET (1<<0) |
| 400 | |
| 401 | #define GLPCI_REN MSR_PCI + 0x2014 |
| 402 | #define GLPCI_A0_BF MSR_PCI + 0x2015 |
| 403 | #define GLPCI_C0_DF MSR_PCI + 0x2016 |
| 404 | #define GLPCI_E0_FF MSR_PCI + 0x2017 |
| 405 | #define GLPCI_RC0 MSR_PCI + 0x2018 |
| 406 | #define GLPCI_RC1 MSR_PCI + 0x2019 |
| 407 | #define GLPCI_RC2 MSR_PCI + 0x201A |
| 408 | #define GLPCI_RC3 MSR_PCI + 0x201B |
| 409 | #define GLPCI_RC4 MSR_PCI + 0x201C |
| 410 | #define GLPCI_RC_UPPER_TOP_SHIFT 12 |
| 411 | #define GLPCI_RC_LOWER_BASE_SHIFT 12 |
| 412 | #define GLPCI_RC_LOWER_EN_SET (1<<8) |
| 413 | #define GLPCI_RC_LOWER_PF_SET (1<<5) |
| 414 | #define GLPCI_RC_LOWER_WC_SET (1<<4) |
| 415 | #define GLPCI_RC_LOWER_WP_SET (1<<2) |
| 416 | #define GLPCI_RC_LOWER_CD_SET (1<<0) |
| 417 | #define GLPCI_ExtMSR MSR_PCI + 0x201E |
| 418 | #define GLPCI_SPARE MSR_PCI + 0x201F |
| 419 | #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) |
| 420 | #define GLPCI_SPARE_LOWER_PPD_SET (1<<5) |
| 421 | #define GLPCI_SPARE_LOWER_PPC_SET (1<<4) |
| 422 | #define GLPCI_SPARE_LOWER_MPC_SET (1<<3) |
| 423 | #define GLPCI_SPARE_LOWER_MME_SET (1<<2) |
| 424 | #define GLPCI_SPARE_LOWER_NSE_SET (1<<1) |
| 425 | #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) |
| 426 | |
| 427 | |
| 428 | /**/ |
| 429 | /* FooGlue GLIU1 port 5*/ |
| 430 | /**/ |
| 431 | #define FG_GLD_MSR_CAP MSR_FG + 0x2000 |
| 432 | #define FG_GLD_MSR_PM MSR_FG + 0x2004 |
| 433 | |
Ronald G. Minnich | 40fedaf | 2006-04-06 23:35:52 +0000 | [diff] [blame^] | 434 | /* VIP GLIU1 port 5*/ |
| 435 | /* */ |
| 436 | #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) |
| 437 | #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) |
| 438 | #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) |
| 439 | #define VIP_BIST (MSR_VIP + 0x2005) |
| 440 | /* */ |
| 441 | /* AES GLIU1 port 6*/ |
| 442 | /* */ |
| 443 | #define AES_GLD_MSR_CAP (MSR_AES + 0x2000) |
| 444 | #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) |
| 445 | #define AES_GLD_MSR_PM (MSR_AES + 0x2004) |
| 446 | #define AES_CONTROL (MSR_AES + 0x2006) |
| 447 | /* more fun stuff */ |
| 448 | #define BM 1 /* Base Mask - map power of 2 size aligned region*/ |
| 449 | #define BMO 2 /* BM with an offset*/ |
| 450 | #define R 3 /* Range - 4k range minimum*/ |
| 451 | #define RO 4 /* R with offset*/ |
| 452 | #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ |
| 453 | #define BMIO 6 /* Base Mask IO*/ |
| 454 | #define SCIO 7 /* Swiss 0xCeese IO*/ |
| 455 | #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/ |
| 456 | #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/ |
| 457 | #define BMO_SMM 10 /* Specail marker for SMM*/ |
| 458 | #define BM_SMM 11 /* Specail marker for SMM*/ |
| 459 | #define BMO_DMM 12 /* Specail marker for DMM*/ |
| 460 | #define BM_DMM 13 /* Specail marker for DMM*/ |
| 461 | #define RO_FB 14 /* special for Frame buffer.*/ |
| 462 | #define R_FB 15 /* special for FB.*/ |
| 463 | #define OTHER 0x0FE /* Special marker for other*/ |
| 464 | #define GL_END 0x0FF /* end*/ |
| 465 | |
| 466 | #define MSR_GL0 (GL1_GLIU0 << 29) |
| 467 | |
| 468 | /* Set up desc addresses from 20 - 3f*/ |
| 469 | /* This is chip specific!*/ |
| 470 | #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/ |
| 471 | #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/ |
| 472 | #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/ |
| 473 | #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/ |
| 474 | #define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/ |
| 475 | #define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/ |
| 476 | |
| 477 | #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/ |
| 478 | #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/ |
| 479 | #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/ |
| 480 | #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/ |
| 481 | #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/ |
| 482 | #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/ |
| 483 | #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/ |
| 484 | |
| 485 | /* definitions that are "once you are mostly up, start VSA" type things */ |
| 486 | #define SMM_OFFSET 0x40400000 |
| 487 | #define SMM_SIZE 256 |
| 488 | #define DMM_OFFSET 0x0C0000000 |
| 489 | #define DMM_SIZE 128 |
| 490 | #define FB_OFFSET 0x41000000 |
| 491 | #define PCI_MEM_TOP 0x0EFFFFFFF // Top of PCI mem allocation region |
| 492 | #define PCI_IO_TOP 0x0EFFF // Top of PCI I/O allocation region |
| 493 | #define END_OPTIONROM_SPACE 0x0DFFF // E0000 is reserved for SystemROMs. |
| 494 | |
| 495 | #define MDD_SMBUS 0x06000 // SMBUS IO location |
| 496 | #define MDD_GPIO 0x06100 // GPIO & ICF IO location |
| 497 | #define MDD_MFGPT 0x06200 // General Purpose Timers IO location |
| 498 | #define MDD_IRQ_MAPPER 0x06300 // IRQ Mapper |
| 499 | #define ACPI_BASE 0x09C00 // ACPI Base |
| 500 | #define MDD_PM 0x09D00 // Power Management Logic - placed at the end of ACPI |
| 501 | |
| 502 | #define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 |
| 503 | #define CHIPSET_DEV_NUM 15 |
| 504 | #define IDSEL_BASE 11 // bit 11 = device 1 |
| 505 | #define SB_PORT 2 // port of the SouthBridge |
| 506 | |
| 507 | /* standard AMD post definitions -- might as well use them. */ |
| 508 | #define POST_Output_Port (0x080) /* port to write post codes to*/ |
| 509 | |
| 510 | #define POST_preSioInit (0x000) /* geode.asm*/ |
| 511 | #define POST_clockInit (0x001) /* geode.asm*/ |
| 512 | #define POST_CPURegInit (0x002) /* geode.asm*/ |
| 513 | #define POST_UNREAL (0x003) /* geode.asm*/ |
| 514 | #define POST_CPUMemRegInit (0x004) /* geode.asm*/ |
| 515 | #define POST_CPUTest (0x005) /* geode.asm*/ |
| 516 | #define POST_memSetup (0x006) /* geode.asm*/ |
| 517 | #define POST_memSetUpStack (0x007) /* geode.asm*/ |
| 518 | #define POST_memTest (0x008) /* geode.asm*/ |
| 519 | #define POST_shadowRom (0x009) /* geode.asm*/ |
| 520 | #define POST_memRAMoptimize (0x00A) /* geode.asm*/ |
| 521 | #define POST_cacheInit (0x00B) /* geode.asm*/ |
| 522 | #define POST_northBridgeInit (0x00C) /* geode.asm*/ |
| 523 | #define POST_chipsetInit (0x00D) /* geode.asm*/ |
| 524 | #define POST_sioTest (0x00E) /* geode.asm*/ |
| 525 | #define POST_pcATjunk (0x00F) /* geode.asm*/ |
| 526 | |
| 527 | |
| 528 | #define POST_intTable (0x010) /* geode.asm*/ |
| 529 | #define POST_memInfo (0x011) /* geode.asm*/ |
| 530 | #define POST_romCopy (0x012) /* geode.asm*/ |
| 531 | #define POST_PLLCheck (0x013) /* geode.asm*/ |
| 532 | #define POST_keyboardInit (0x014) /* geode.asm*/ |
| 533 | #define POST_cpuCacheOff (0x015) /* geode.asm*/ |
| 534 | #define POST_BDAInit (0x016) /* geode.asm*/ |
| 535 | #define POST_pciScan (0x017) /* geode.asm*/ |
| 536 | #define POST_optionRomInit (0x018) /* geode.asm*/ |
| 537 | #define POST_ResetLimits (0x019) /* geode.asm*/ |
| 538 | #define POST_summary_screen (0x01A) /* geode.asm*/ |
| 539 | #define POST_Boot (0x01B) /* geode.asm*/ |
| 540 | #define POST_SystemPreInit (0x01C) /* geode.asm*/ |
| 541 | #define POST_ClearRebootFlag (0x01D) /* geode.asm*/ |
| 542 | #define POST_GLIUInit (0x01E) /* geode.asm*/ |
| 543 | #define POST_BootFailed (0x01F) /* geode.asm*/ |
| 544 | |
| 545 | |
| 546 | #define POST_CPU_ID (0x020) /* cpucpuid.asm*/ |
| 547 | #define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ |
| 548 | #define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ |
| 549 | #define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ |
| 550 | #define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ |
| 551 | #define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ |
| 552 | #define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ |
| 553 | #define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ |
| 554 | #define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ |
| 555 | #define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ |
| 556 | #define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ |
| 557 | #define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ |
| 558 | #define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ |
| 559 | #define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ |
| 560 | #define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ |
| 561 | #define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ |
| 562 | |
| 563 | |
| 564 | |
| 565 | /* PCI config*/ |
| 566 | #define P80_PCICFG (0x030) /* pcispace.asm*/ |
| 567 | |
| 568 | |
| 569 | /* PCI io*/ |
| 570 | #define P80_PCIIO (0x040) /* pcispace.asm*/ |
| 571 | |
| 572 | |
| 573 | /* PCI memory*/ |
| 574 | #define P80_PCIMEM (0x050) /* pcispace.asm*/ |
| 575 | |
| 576 | |
| 577 | /* SIO*/ |
| 578 | #define P80_SIO (0x060) /* *sio.asm*/ |
| 579 | |
| 580 | /* Memory Setp*/ |
| 581 | #define P80_MEM_SETUP (0x070) /* docboot meminit*/ |
| 582 | #define POST_MEM_SETUP (0x070) /* memsize.asm*/ |
| 583 | #define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ |
| 584 | #define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ |
| 585 | #define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ |
| 586 | #define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ |
| 587 | #define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ |
| 588 | #define POST_MEM_ENABLE (0x076) /* memsize.asm*/ |
| 589 | #define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ |
| 590 | #define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ |
| 591 | #define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ |
| 592 | #define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ |
| 593 | #define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ |
| 594 | #define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ |
| 595 | #define ERROR_BANK_SET (0x07d) /* memsize.asm*/ |
| 596 | #define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ |
| 597 | #define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ |
| 598 | |
| 599 | |
| 600 | #define POST_UserPreInit (0x080) /* geode.asm*/ |
| 601 | #define POST_UserPostInit (0x081) /* geode.asm*/ |
| 602 | #define POST_Equipment_check (0x082) /* geode.asm*/ |
| 603 | #define POST_InitNVRAMBX (0x083) /* geode.asm*/ |
| 604 | #define POST_NoPIRTable (0x084) /* pci.asm*/ |
| 605 | #define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ |
| 606 | #define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ |
| 607 | #define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ |
| 608 | #define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ |
| 609 | #define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ |
| 610 | #define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ |
| 611 | #define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ |
| 612 | #define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ |
| 613 | #define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ |
| 614 | #define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ |
| 615 | |
| 616 | |
| 617 | #define POST_STACK_SETUP (0x090) /* memstack.asm*/ |
| 618 | #define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ |
| 619 | #define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ |
| 620 | #define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ |
| 621 | #define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ |
| 622 | #define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ |
| 623 | #define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ |
| 624 | #define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ |
| 625 | #define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ |
| 626 | |
| 627 | |
| 628 | #define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ |
| 629 | #define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ |
| 630 | #define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ |
| 631 | #define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ |
| 632 | #define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ |
| 633 | #define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ |
| 634 | #define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ |
| 635 | |
| 636 | |
| 637 | #define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ |
| 638 | #define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ |
| 639 | #define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ |
| 640 | #define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ |
| 641 | #define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ |
| 642 | #define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ |
| 643 | #define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ |
| 644 | |
| 645 | |
| 646 | #define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ |
| 647 | #define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ |
| 648 | #define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ |
| 649 | #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ |
| 650 | #define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ |
| 651 | #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ |
| 652 | #define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ |
| 653 | #define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ |
| 654 | #define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ |
| 655 | #define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ |
| 656 | #define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ |
| 657 | #define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ |
| 658 | #define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ |
| 659 | #define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ |
| 660 | |
| 661 | #define POST_RCONFInitError (0x0CE) /* cache.asm*/ |
| 662 | #define POST_CacheInitError (0x0CF) /* cache.asm*/ |
| 663 | |
| 664 | |
| 665 | #define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ |
| 666 | #define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ |
| 667 | #define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ |
| 668 | #define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ |
| 669 | #define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ |
| 670 | #define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ |
| 671 | #define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ |
| 672 | #define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ |
| 673 | #define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ |
| 674 | #define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ |
| 675 | #define POST_ROM_POSTUNCOMPRESS (0x0DE) |
| 676 | |
| 677 | |
| 678 | #define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ |
| 679 | #define POST_PreChipsetInit (0x0E1) /* geode.asm*/ |
| 680 | #define POST_LateChipsetInit (0x0E2) /* geode.asm*/ |
| 681 | #define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ |
| 682 | |
| 683 | |
| 684 | #define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ |
| 685 | |
Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame] | 686 | #endif /* CPU_AMD_GX2DEF_H */ |