| Li-Ta Lo | 71eae20 | 2006-03-13 21:58:43 +0000 | [diff] [blame^] | 1 | #ifndef CPU_AMD_GX2DEF_H |
| 2 | #define CPU_AMD_GX2DEF_H |
| 3 | |
| 4 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ |
| 5 | #define GLCP_CLK_DIS_DELAY 0x4c000008 |
| 6 | #define GLCP_PMCLKDISABLE 0x4c000009 |
| 7 | #define GLCP_DELAY_CONTROLS 0x4c00000f |
| 8 | #define GLCP_SYS_RSTPLL 0x4c000014 |
| 9 | #define GLCP_DOTPLL 0x4c000015 |
| 10 | |
| 11 | |
| 12 | /* Upper 32 bits */ |
| 13 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 14 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 15 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
| 16 | |
| 17 | /* Lower 32 bits */ |
| 18 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 19 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 20 | |
| 21 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 22 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 23 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 24 | #define GLCP_SYS_RSTPLL_PD 14 |
| 25 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 26 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 27 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 28 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 29 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
| 30 | |
| 31 | #endif /* CPU_AMD_GX2DEF_H */ |