Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Michał Żygowski | f65c1e4 | 2019-12-01 18:14:39 +0100 | [diff] [blame] | 5 | #include <amdblocks/biosram.h> |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 6 | #include <amdblocks/hda.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 8 | #include <arch/hpet.h> |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 9 | #include <arch/ioapic.h> |
Felix Held | a8da070 | 2023-06-05 21:19:27 +0200 | [diff] [blame] | 10 | #include <arch/vga.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 11 | #include <acpi/acpi.h> |
| 12 | #include <acpi/acpigen.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 13 | #include <cbmem.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 14 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 15 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 16 | #include <cpu/x86/lapic_def.h> |
Marshall Dawson | f82aa10 | 2017-09-20 18:01:41 -0600 | [diff] [blame] | 17 | #include <cpu/x86/msr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 21 | #include <amdblocks/agesawrapper.h> |
| 22 | #include <amdblocks/agesawrapper_call.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 23 | #include <amdblocks/ioapic.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 24 | #include <agesa_headers.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 25 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 26 | #include <soc/northbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 28 | #include <soc/iomap.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | #include <stdint.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 30 | #include <string.h> |
| 31 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 32 | #include "chip.h" |
| 33 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 34 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 35 | u32 io_min, u32 io_max) |
| 36 | { |
| 37 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 38 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 39 | /* io range allocation. Limit */ |
| 40 | tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
| 41 | | ((io_max & 0xf0) << (12 - 4)); |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 42 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 43 | tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 44 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 45 | } |
| 46 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 47 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, |
| 48 | u32 mmio_min, u32 mmio_max) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 49 | { |
| 50 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 51 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 52 | /* io range allocation. Limit */ |
| 53 | tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); |
Felix Held | aec49ae | 2023-04-19 21:42:46 +0200 | [diff] [blame] | 54 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 55 | tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); |
Felix Held | aec49ae | 2023-04-19 21:42:46 +0200 | [diff] [blame] | 56 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 57 | } |
| 58 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 59 | static void read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 60 | { |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 61 | unsigned int idx = 0; |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 62 | |
Felix Held | af17f0b | 2022-03-02 23:36:55 +0100 | [diff] [blame] | 63 | /* The northbridge has no PCI BARs implemented, so there's no need to call |
| 64 | pci_dev_read_resources for it */ |
| 65 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 66 | /* |
| 67 | * This MMCONF resource must be reserved in the PCI domain. |
| 68 | * It is not honored by the coreboot resource allocator if it is in |
| 69 | * the CPU_CLUSTER. |
| 70 | */ |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 71 | mmconf_resource(dev, idx++); |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 72 | |
| 73 | /* NB IOAPIC2 resource */ |
Felix Held | 8f0075c | 2023-08-09 19:28:39 +0200 | [diff] [blame] | 74 | mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 75 | } |
| 76 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 77 | static void set_resource(struct device *dev, struct resource *res, u32 nodeid) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 78 | { |
| 79 | resource_t rbase, rend; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 80 | unsigned int reg, link_num; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 81 | char buf[50]; |
| 82 | |
| 83 | /* Make certain the resource has actually been set */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 84 | if (!(res->flags & IORESOURCE_ASSIGNED)) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 85 | return; |
| 86 | |
| 87 | /* If I have already stored this resource don't worry about it */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 88 | if (res->flags & IORESOURCE_STORED) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 89 | return; |
| 90 | |
| 91 | /* Only handle PCI memory and IO resources */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 92 | if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 93 | return; |
| 94 | |
| 95 | /* Ensure I am actually looking at a resource of function 1 */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 96 | if ((res->index & 0xffff) < 0x1000) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 97 | return; |
| 98 | |
| 99 | /* Get the base address */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 100 | rbase = res->base; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 101 | |
| 102 | /* Get the limit (rounded up) */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 103 | rend = resource_end(res); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 104 | |
| 105 | /* Get the register and link */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 106 | reg = res->index & 0xfff; /* 4k */ |
| 107 | link_num = IOINDEX_LINK(res->index); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 108 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 109 | if (res->flags & IORESOURCE_IO) |
Elyes Haouas | 55d0f40 | 2022-07-16 09:53:05 +0200 | [diff] [blame] | 110 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 111 | else if (res->flags & IORESOURCE_MEM) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 112 | set_mmio_addr_reg(nodeid, link_num, reg, |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 113 | (res->index >> 24), rbase >> 8, rend >> 8); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 114 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 115 | res->flags |= IORESOURCE_STORED; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 116 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
| 117 | nodeid, link_num); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 118 | report_resource_stored(dev, res, buf); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | /** |
| 122 | * I tried to reuse the resource allocation code in set_resource() |
| 123 | * but it is too difficult to deal with the resource allocation magic. |
| 124 | */ |
| 125 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 126 | static void create_vga_resource(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 127 | { |
| 128 | struct bus *link; |
| 129 | |
| 130 | /* find out which link the VGA card is connected, |
| 131 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 132 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 133 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 134 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 135 | |
| 136 | /* no VGA card installed */ |
| 137 | if (link == NULL) |
| 138 | return; |
| 139 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 140 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 141 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 142 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 143 | } |
| 144 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 145 | static void set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | { |
| 147 | struct bus *bus; |
| 148 | struct resource *res; |
| 149 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 150 | /* do we need this? */ |
| 151 | create_vga_resource(dev); |
| 152 | |
| 153 | /* Set each resource we have found */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 154 | for (res = dev->resource_list ; res ; res = res->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 155 | set_resource(dev, res, 0); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 156 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 157 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 158 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 159 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | static void northbridge_init(struct device *dev) |
| 163 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 164 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 165 | } |
| 166 | |
Felix Held | 8cab80c | 2023-05-05 15:20:15 +0200 | [diff] [blame] | 167 | /* Used by \_SB.PCI0._CRS */ |
| 168 | static void acpi_fill_root_complex_tom(const struct device *device) |
| 169 | { |
| 170 | const char *scope; |
| 171 | |
| 172 | assert(device); |
| 173 | |
| 174 | scope = acpi_device_scope(device); |
| 175 | assert(scope); |
| 176 | acpigen_write_scope(scope); |
| 177 | |
| 178 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 179 | |
| 180 | /* |
| 181 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 182 | * here. |
| 183 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 184 | * slide 22ff. |
| 185 | * Shift value right by 20 bit to make it fit into 32bit, |
| 186 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 187 | */ |
| 188 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
| 189 | acpigen_pop_len(); |
| 190 | } |
| 191 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 192 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 193 | { |
| 194 | void *addr, *current; |
| 195 | |
| 196 | /* Skip the HEST header. */ |
| 197 | current = (void *)(hest + 1); |
| 198 | |
| 199 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 200 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 201 | current += acpi_create_hest_error_source(hest, current, 0, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 202 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 203 | |
| 204 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 205 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 206 | current += acpi_create_hest_error_source(hest, current, 1, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 207 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 208 | |
| 209 | return (unsigned long)current; |
| 210 | } |
| 211 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 212 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 213 | unsigned long current, |
| 214 | acpi_rsdp_t *rsdp) |
| 215 | { |
| 216 | acpi_srat_t *srat; |
| 217 | acpi_slit_t *slit; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 218 | acpi_header_t *alib; |
| 219 | acpi_header_t *ivrs; |
| 220 | acpi_hest_t *hest; |
| 221 | |
| 222 | /* HEST */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 223 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 224 | hest = (acpi_hest_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 225 | acpi_write_hest(hest, acpi_fill_hest); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 226 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 227 | current += hest->header.length; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 228 | |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 229 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 230 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 231 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 232 | if (ivrs != NULL) { |
| 233 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 234 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 235 | current += ivrs->length; |
| 236 | acpi_add_table(rsdp, ivrs); |
| 237 | } else { |
| 238 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 239 | } |
| 240 | |
| 241 | /* SRAT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 242 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 243 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 244 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 245 | if (srat != NULL) { |
| 246 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 247 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 248 | current += srat->header.length; |
| 249 | acpi_add_table(rsdp, srat); |
| 250 | } else { |
| 251 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 252 | } |
| 253 | |
| 254 | /* SLIT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 255 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 256 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 257 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 258 | if (slit != NULL) { |
| 259 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 260 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 261 | current += slit->header.length; |
| 262 | acpi_add_table(rsdp, slit); |
| 263 | } else { |
| 264 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 265 | } |
| 266 | |
| 267 | /* ALIB */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 268 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 269 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 270 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 271 | if (alib != NULL) { |
| 272 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 273 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 274 | current += alib->length; |
| 275 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 276 | } else { |
| 277 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 278 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 279 | } |
| 280 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 281 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 282 | return current; |
| 283 | } |
| 284 | |
Felix Held | 26651c8 | 2022-10-13 16:12:40 +0200 | [diff] [blame] | 285 | struct device_operations stoneyridge_northbridge_operations = { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 286 | .read_resources = read_resources, |
| 287 | .set_resources = set_resources, |
| 288 | .enable_resources = pci_dev_enable_resources, |
| 289 | .init = northbridge_init, |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 290 | .acpi_fill_ssdt = acpi_fill_root_complex_tom, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 291 | .write_acpi_tables = agesa_write_acpi_tables, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 292 | }; |
| 293 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 294 | /* |
| 295 | * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, |
| 296 | * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining |
| 297 | * MMIO to posted. Route all I/O to the southbridge. |
| 298 | */ |
| 299 | void amd_initcpuio(void) |
| 300 | { |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 301 | uintptr_t topmem = get_top_of_mem_below_4gb(); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 302 | uintptr_t base, limit; |
| 303 | |
| 304 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 305 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
| 306 | |
| 307 | /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ |
| 308 | base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; |
Kyösti Mälkki | dea42e0 | 2021-05-31 20:26:16 +0300 | [diff] [blame] | 309 | limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 310 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); |
| 311 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |
| 312 | |
| 313 | /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ |
| 314 | base = (topmem >> 8) | MMIO_WE | MMIO_RE; |
| 315 | limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; |
| 316 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); |
| 317 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); |
| 318 | |
| 319 | /* Route all I/O downstream */ |
| 320 | base = 0 | IO_WE | IO_RE; |
| 321 | limit = ALIGN_DOWN(0xffff, 4 * KiB); |
| 322 | pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); |
| 323 | pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); |
| 324 | } |
| 325 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 326 | void fam15_finalize(void *chip_info) |
| 327 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 328 | u32 value; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 329 | |
| 330 | /* TODO: move IOAPIC code to dsdt.asl */ |
| 331 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); |
| 332 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 333 | |
| 334 | /* disable No Snoop */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 335 | value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); |
Richard Spiegel | 3d34ae3 | 2018-04-13 13:20:08 -0700 | [diff] [blame] | 336 | value &= ~HDA_NO_SNOOP_EN; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 337 | pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 338 | } |
| 339 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 340 | void domain_enable_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 341 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 342 | /* Must be called after PCI enumeration and resource allocation */ |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 343 | if (!acpi_is_wakeup_s3()) |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 344 | do_agesawrapper(AMD_INIT_MID, "amdinitmid"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 345 | } |
| 346 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 347 | void domain_read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 348 | { |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 349 | uint64_t uma_base = get_uma_base(); |
| 350 | uint32_t uma_size = get_uma_size(); |
| 351 | uint32_t mem_useable = (uintptr_t)cbmem_top(); |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 352 | uint32_t tom = get_top_of_mem_below_4gb(); |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 353 | uint64_t high_tom = get_top_of_mem_above_4gb(); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 354 | uint64_t high_mem_useable; |
| 355 | int idx = 0x10; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 356 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 357 | pci_domain_read_resources(dev); |
| 358 | |
Felix Held | d7ad140 | 2023-06-05 15:30:10 +0200 | [diff] [blame] | 359 | fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
| 360 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 361 | /* 0x0 -> 0x9ffff */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 362 | ram_range(dev, idx++, 0, 0xa0000); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 363 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 364 | /* 0xa0000 -> 0xbffff: legacy VGA */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 365 | mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 366 | |
| 367 | /* 0xc0000 -> 0xfffff: Option ROM */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 368 | reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 369 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 370 | /* |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 371 | * 0x100000 (1MiB) -> low top usable RAM |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 372 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 373 | */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 374 | ram_from_to(dev, idx++, 1 * MiB, mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 375 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 376 | /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 377 | reserved_ram_from_to(dev, idx++, mem_useable, tom); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 378 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 379 | /* If there is memory above 4GiB */ |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 380 | if (high_tom >> 32) { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 381 | /* 4GiB -> high top usable */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 382 | if (uma_base >= (4ull * GiB)) |
| 383 | high_mem_useable = uma_base; |
| 384 | else |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 385 | high_mem_useable = high_tom; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 386 | |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 387 | ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 388 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 389 | /* High top usable RAM -> high top RAM */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 390 | if (uma_base >= (4ull * GiB)) { |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 391 | reserved_ram_range(dev, idx++, uma_base, uma_size); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 392 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 393 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 394 | } |
| 395 | |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 396 | __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } |
| 397 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 398 | void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) |
| 399 | { |
Martin Roth | 50f2e4c | 2018-10-29 11:16:53 -0600 | [diff] [blame] | 400 | const struct device *dev = SOC_IOMMU_DEV; |
| 401 | params->IommuSupport = dev && dev->enabled; |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 402 | set_board_env_params(params); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | void SetNbMidParams(GNB_MID_CONFIGURATION *params) |
| 406 | { |
| 407 | /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ |
| 408 | params->iGpuVgaMode = 0; |
| 409 | params->GnbIoapicAddress = IO_APIC2_ADDR; |
| 410 | } |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 411 | |
| 412 | void hda_soc_ssdt_quirks(const struct device *dev) |
| 413 | { |
| 414 | const char *scope = acpi_device_path(dev); |
| 415 | static const struct fieldlist list[] = { |
| 416 | FIELDLIST_OFFSET(0x42), |
| 417 | FIELDLIST_NAMESTR("NSDI", 1), |
| 418 | FIELDLIST_NAMESTR("NSDO", 1), |
| 419 | FIELDLIST_NAMESTR("NSEN", 1), |
| 420 | }; |
| 421 | struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100); |
| 422 | |
| 423 | assert(scope); |
| 424 | |
| 425 | acpigen_write_scope(scope); |
| 426 | |
| 427 | /* |
| 428 | * OperationRegion(AZPD, PCI_Config, 0x00, 0x100) |
| 429 | * Field (AZPD, AnyAcc, NoLock, Preserve) { |
| 430 | * Offset (0x42), |
| 431 | * NSDI, 1, |
| 432 | * NSDO, 1, |
| 433 | * NSEN, 1, |
| 434 | * } |
| 435 | */ |
| 436 | acpigen_write_opregion(&opreg); |
| 437 | acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), |
| 438 | FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 439 | |
| 440 | /* |
| 441 | * Method (_INI, 0, NotSerialized) { |
Kyösti Mälkki | ff9ba54 | 2021-02-09 17:38:23 +0200 | [diff] [blame] | 442 | * Store (Zero, NSEN) |
| 443 | * Store (One, NSDO) |
| 444 | * Store (One, NSDI) |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 445 | * } |
| 446 | */ |
| 447 | acpigen_write_method("_INI", 0); |
| 448 | |
Furquan Shaikh | ac204ba | 2021-02-19 10:23:17 -0800 | [diff] [blame] | 449 | acpigen_write_store_op_to_namestr(ZERO_OP, "NSEN"); |
| 450 | acpigen_write_store_op_to_namestr(ONE_OP, "NSDO"); |
| 451 | acpigen_write_store_op_to_namestr(ONE_OP, "NSDI"); |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 452 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 453 | acpigen_pop_len(); /* Method _INI */ |
| 454 | |
| 455 | acpigen_pop_len(); /* Scope */ |
| 456 | } |