soc/amd/*/northbridge,root_complex: simplify mmconf_resource index
In the northbridge's and root complex' read_resources function, the
mmconf resource used the number of the MMIO_CONF_BASE MSR as index which
might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 04472dc..0a80648 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -57,6 +57,7 @@
static void read_resources(struct device *dev)
{
+ unsigned int idx = 0;
struct resource *res;
/*
@@ -64,7 +65,7 @@
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- mmconf_resource(dev, MMIO_CONF_BASE);
+ mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */
res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */