commit 392cf2f8f842b3d1705927e9b784032d88296a0d
author Felix Held <felix-coreboot@felixheld.de> Thu Apr 20 13:23:23 2023 +0200
committer Felix Held <felix-coreboot@felixheld.de> Fri Apr 21 15:14:18 2023 +0000
tree 7377f924c6dce491ceec5fc7d08db07588dd0b2d
parent 09906111aaaa2a74e67b2483ee9dd7e0fbbddf2b

soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb

Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of
open-coding the functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/stoneyridge/northbridge.c

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index ccfa9cb..bafeabb 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -327,8 +327,8 @@
 	uint64_t uma_base = get_uma_base();
 	uint32_t uma_size = get_uma_size();
 	uint32_t mem_useable = (uintptr_t)cbmem_top();
-	msr_t tom = rdmsr(TOP_MEM);
-	msr_t high_tom = rdmsr(TOP_MEM2);
+	uint32_t tom = get_top_of_mem_below_4gb();
+	uint64_t high_tom = get_top_of_mem_above_4g();
 	uint64_t high_mem_useable;
 	int idx = 0x10;
 
@@ -352,16 +352,15 @@
 
 	/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
 	reserved_ram_resource_kb(dev, idx++, mem_useable / KiB,
-					(tom.lo - mem_useable) / KiB);
+					(tom - mem_useable) / KiB);
 
 	/* If there is memory above 4GiB */
-	if (high_tom.hi) {
+	if (high_tom >> 32) {
 		/* 4GiB -> high top usable */
 		if (uma_base >= (4ull * GiB))
 			high_mem_useable = uma_base;
 		else
-			high_mem_useable = ((uint64_t)high_tom.lo |
-						((uint64_t)high_tom.hi << 32));
+			high_mem_useable = high_tom;
 
 		ram_resource_kb(dev, idx++, (4ull * GiB) / KiB,
 				((high_mem_useable - (4ull * GiB)) / KiB));