Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/acpigen.h> |
| 20 | #include <cbmem.h> |
| 21 | #include <chip.h> |
| 22 | #include <console/console.h> |
| 23 | #include <cpu/amd/amdfam15.h> |
| 24 | #include <cpu/amd/mtrr.h> |
| 25 | #include <cpu/cpu.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <device/pci_ids.h> |
| 29 | #include <device/hypertransport.h> |
| 30 | #include <lib.h> |
| 31 | #include <agesawrapper.h> |
| 32 | #include <agesawrapper_call.h> |
| 33 | #include <soc/northbridge.h> |
| 34 | #include <stdint.h> |
| 35 | #include <stdlib.h> |
| 36 | #include <string.h> |
| 37 | |
| 38 | /* |
| 39 | * AMD vendorcode files. Place at the end so coreboot defaults and maintained |
| 40 | * and not set by vendorcode |
| 41 | */ |
| 42 | #include <AGESA.h> |
| 43 | #include <cpuRegisters.h> |
| 44 | #include <FieldAccessors.h> |
| 45 | #include <Options.h> |
| 46 | #include <Porting.h> |
| 47 | #include <Topology.h> |
| 48 | |
| 49 | #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) |
| 50 | |
| 51 | #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 |
| 52 | #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! |
| 53 | #endif |
| 54 | |
| 55 | typedef struct dram_base_mask { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 56 | u32 base; /* [47:27] at [28:8] */ |
| 57 | u32 mask; /* [47:27] at [28:8] and enable at bit 0 */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 58 | } dram_base_mask_t; |
| 59 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 60 | static unsigned int node_nums; |
| 61 | static unsigned int sblink; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 62 | static device_t __f0_dev; |
| 63 | static device_t __f1_dev; |
| 64 | static device_t __f2_dev; |
| 65 | static device_t __f4_dev; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 66 | static unsigned int fx_dev = 0; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 67 | |
| 68 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 69 | { |
| 70 | device_t dev = __f1_dev; |
| 71 | dram_base_mask_t d; |
| 72 | u32 temp; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 73 | |
| 74 | /* [39:24] at [31:16] */ |
| 75 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); |
| 76 | |
| 77 | /* mask out DramMask [26:24] too */ |
| 78 | d.mask = ((temp & 0xfff80000) >> (8 + 3)); |
| 79 | |
| 80 | /* [47:40] at [7:0] */ |
| 81 | temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 82 | d.mask |= temp << 21; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 83 | |
| 84 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); |
| 85 | d.mask |= (temp & 1); /* enable bit */ |
| 86 | d.base = ((temp & 0xfff80000) >> (8 + 3)); |
| 87 | temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 88 | d.base |= temp << 21; |
| 89 | return d; |
| 90 | } |
| 91 | |
| 92 | static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, |
| 93 | u32 io_min, u32 io_max) |
| 94 | { |
| 95 | u32 tempreg; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 96 | /* io range allocation. Limit */ |
| 97 | tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
| 98 | | ((io_max & 0xf0) << (12 - 4)); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 99 | pci_write_config32(__f1_dev, reg + 4, tempreg); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 100 | tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 101 | pci_write_config32(__f1_dev, reg, tempreg); |
| 102 | } |
| 103 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 104 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, |
| 105 | u32 mmio_min, u32 mmio_max) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 106 | { |
| 107 | u32 tempreg; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 108 | /* io range allocation. Limit */ |
| 109 | tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 110 | pci_write_config32(__f1_dev, reg + 4, tempreg); |
| 111 | tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); |
| 112 | pci_write_config32(__f1_dev, reg, tempreg); |
| 113 | } |
| 114 | |
| 115 | static device_t get_node_pci(u32 fn) |
| 116 | { |
| 117 | return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, fn)); |
| 118 | } |
| 119 | |
| 120 | static void get_fx_dev(void) |
| 121 | { |
| 122 | __f0_dev = get_node_pci(0); |
| 123 | __f1_dev = get_node_pci(1); |
| 124 | __f2_dev = get_node_pci(2); |
| 125 | __f4_dev = get_node_pci(4); |
| 126 | fx_dev = 1; |
| 127 | |
| 128 | if (__f1_dev == NULL || __f0_dev == NULL || fx_dev == 0) |
| 129 | die("Cannot find 0:0x18.[0|1]\n"); |
| 130 | } |
| 131 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 132 | static u32 f1_read_config32(unsigned int reg) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 133 | { |
| 134 | if (fx_dev == 0) |
| 135 | get_fx_dev(); |
| 136 | return pci_read_config32(__f1_dev, reg); |
| 137 | } |
| 138 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 139 | static void f1_write_config32(unsigned int reg, u32 value) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 140 | { |
| 141 | if (fx_dev == 0) |
| 142 | get_fx_dev(); |
| 143 | pci_write_config32(__f1_dev, reg, value); |
| 144 | } |
| 145 | |
| 146 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 147 | { |
| 148 | u32 val; |
| 149 | |
| 150 | val = 1 | (nodeid << 4) | (linkn << 12); |
| 151 | /* Routes: |
| 152 | * mmio 0xa0000:0xbffff |
| 153 | * io 0x3b0:0x3bb, 0x3c0:0x3df |
| 154 | */ |
| 155 | f1_write_config32(0xf4, val); |
| 156 | } |
| 157 | |
| 158 | static void read_resources(device_t dev) |
| 159 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 160 | /* |
| 161 | * This MMCONF resource must be reserved in the PCI domain. |
| 162 | * It is not honored by the coreboot resource allocator if it is in |
| 163 | * the CPU_CLUSTER. |
| 164 | */ |
| 165 | mmconf_resource(dev, 0xc0010058); |
| 166 | } |
| 167 | |
| 168 | static void set_resource(device_t dev, struct resource *resource, u32 nodeid) |
| 169 | { |
| 170 | resource_t rbase, rend; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 171 | unsigned int reg, link_num; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 172 | char buf[50]; |
| 173 | |
| 174 | /* Make certain the resource has actually been set */ |
| 175 | if (!(resource->flags & IORESOURCE_ASSIGNED)) |
| 176 | return; |
| 177 | |
| 178 | /* If I have already stored this resource don't worry about it */ |
| 179 | if (resource->flags & IORESOURCE_STORED) |
| 180 | return; |
| 181 | |
| 182 | /* Only handle PCI memory and IO resources */ |
| 183 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 184 | return; |
| 185 | |
| 186 | /* Ensure I am actually looking at a resource of function 1 */ |
| 187 | if ((resource->index & 0xffff) < 0x1000) |
| 188 | return; |
| 189 | |
| 190 | /* Get the base address */ |
| 191 | rbase = resource->base; |
| 192 | |
| 193 | /* Get the limit (rounded up) */ |
| 194 | rend = resource_end(resource); |
| 195 | |
| 196 | /* Get the register and link */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 197 | reg = resource->index & 0xfff; /* 4k */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 198 | link_num = IOINDEX_LINK(resource->index); |
| 199 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 200 | if (resource->flags & IORESOURCE_IO) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 201 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 202 | else if (resource->flags & IORESOURCE_MEM) |
| 203 | set_mmio_addr_reg(nodeid, link_num, reg, |
| 204 | (resource->index >> 24), rbase >> 8, rend >> 8); |
| 205 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 206 | resource->flags |= IORESOURCE_STORED; |
| 207 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
| 208 | nodeid, link_num); |
| 209 | report_resource_stored(dev, resource, buf); |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * I tried to reuse the resource allocation code in set_resource() |
| 214 | * but it is too difficult to deal with the resource allocation magic. |
| 215 | */ |
| 216 | |
| 217 | static void create_vga_resource(device_t dev) |
| 218 | { |
| 219 | struct bus *link; |
| 220 | |
| 221 | /* find out which link the VGA card is connected, |
| 222 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 223 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 224 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 225 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 226 | |
| 227 | /* no VGA card installed */ |
| 228 | if (link == NULL) |
| 229 | return; |
| 230 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 231 | printk(BIOS_DEBUG, "VGA: %s link %d has VGA device\n", |
| 232 | dev_path(dev), sblink); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 233 | set_vga_enable_reg(0, sblink); |
| 234 | } |
| 235 | |
| 236 | static void set_resources(device_t dev) |
| 237 | { |
| 238 | struct bus *bus; |
| 239 | struct resource *res; |
| 240 | |
| 241 | |
| 242 | /* do we need this? */ |
| 243 | create_vga_resource(dev); |
| 244 | |
| 245 | /* Set each resource we have found */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 246 | for (res = dev->resource_list ; res ; res = res->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 247 | set_resource(dev, res, 0); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 248 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 249 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 250 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 251 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | static void northbridge_init(struct device *dev) |
| 255 | { |
| 256 | } |
| 257 | |
| 258 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 259 | { |
| 260 | void *addr, *current; |
| 261 | |
| 262 | /* Skip the HEST header. */ |
| 263 | current = (void *)(hest + 1); |
| 264 | |
| 265 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 266 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 267 | current += acpi_create_hest_error_source(hest, current, 0, |
| 268 | (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 269 | |
| 270 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 271 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 272 | current += acpi_create_hest_error_source(hest, current, 1, |
| 273 | (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 274 | |
| 275 | return (unsigned long)current; |
| 276 | } |
| 277 | |
| 278 | static void northbridge_fill_ssdt_generator(device_t device) |
| 279 | { |
| 280 | msr_t msr; |
| 281 | char pscope[] = "\\_SB.PCI0"; |
| 282 | |
| 283 | acpigen_write_scope(pscope); |
| 284 | msr = rdmsr(TOP_MEM); |
| 285 | acpigen_write_name_dword("TOM1", msr.lo); |
| 286 | msr = rdmsr(TOP_MEM2); |
| 287 | /* |
| 288 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 289 | * here. |
| 290 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 291 | * slide 22ff. |
| 292 | * Shift value right by 20 bit to make it fit into 32bit, |
| 293 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 294 | */ |
| 295 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 296 | acpigen_pop_len(); |
| 297 | } |
| 298 | |
| 299 | static unsigned long agesa_write_acpi_tables(device_t device, |
| 300 | unsigned long current, |
| 301 | acpi_rsdp_t *rsdp) |
| 302 | { |
| 303 | acpi_srat_t *srat; |
| 304 | acpi_slit_t *slit; |
| 305 | acpi_header_t *ssdt; |
| 306 | acpi_header_t *alib; |
| 307 | acpi_header_t *ivrs; |
| 308 | acpi_hest_t *hest; |
| 309 | |
| 310 | /* HEST */ |
| 311 | current = ALIGN(current, 8); |
| 312 | hest = (acpi_hest_t *)current; |
| 313 | acpi_write_hest((void *)current, acpi_fill_hest); |
| 314 | acpi_add_table(rsdp, (void *)current); |
| 315 | current += ((acpi_header_t *)current)->length; |
| 316 | |
| 317 | current = ALIGN(current, 8); |
| 318 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 319 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 320 | if (ivrs != NULL) { |
| 321 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 322 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 323 | current += ivrs->length; |
| 324 | acpi_add_table(rsdp, ivrs); |
| 325 | } else { |
| 326 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 327 | } |
| 328 | |
| 329 | /* SRAT */ |
| 330 | current = ALIGN(current, 8); |
| 331 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 332 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 333 | if (srat != NULL) { |
| 334 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 335 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 336 | current += srat->header.length; |
| 337 | acpi_add_table(rsdp, srat); |
| 338 | } else { |
| 339 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 340 | } |
| 341 | |
| 342 | /* SLIT */ |
| 343 | current = ALIGN(current, 8); |
| 344 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 345 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 346 | if (slit != NULL) { |
| 347 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 348 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 349 | current += slit->header.length; |
| 350 | acpi_add_table(rsdp, slit); |
| 351 | } else { |
| 352 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 353 | } |
| 354 | |
| 355 | /* ALIB */ |
| 356 | current = ALIGN(current, 16); |
| 357 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 358 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 359 | if (alib != NULL) { |
| 360 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 361 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 362 | current += alib->length; |
| 363 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 364 | } else { |
| 365 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 366 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 367 | } |
| 368 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 369 | current = ALIGN(current, 16); |
| 370 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 371 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 372 | if (ssdt != NULL) { |
| 373 | memcpy((void *)current, ssdt, ssdt->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 374 | ssdt = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 375 | current += ssdt->length; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 376 | } else { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 377 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 378 | } |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 379 | acpi_add_table(rsdp, ssdt); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 380 | |
| 381 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 382 | return current; |
| 383 | } |
| 384 | |
| 385 | static struct device_operations northbridge_operations = { |
| 386 | .read_resources = read_resources, |
| 387 | .set_resources = set_resources, |
| 388 | .enable_resources = pci_dev_enable_resources, |
| 389 | .init = northbridge_init, |
| 390 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 391 | .write_acpi_tables = agesa_write_acpi_tables, |
| 392 | .enable = 0, |
| 393 | .ops_pci = 0, |
| 394 | }; |
| 395 | |
| 396 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 397 | .ops = &northbridge_operations, |
| 398 | .vendor = PCI_VENDOR_ID_AMD, |
| 399 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, |
| 400 | }; |
| 401 | |
| 402 | void fam15_finalize(void *chip_info) |
| 403 | { |
| 404 | device_t dev; |
| 405 | u32 value; |
| 406 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 407 | pci_write_config32(dev, 0xf8, 0); |
| 408 | pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 409 | |
| 410 | /* disable No Snoop */ |
| 411 | dev = dev_find_slot(0, PCI_DEVFN(1, 1)); |
| 412 | value = pci_read_config32(dev, 0x60); |
| 413 | value &= ~(1 << 11); |
| 414 | pci_write_config32(dev, 0x60, value); |
| 415 | } |
| 416 | |
| 417 | void domain_read_resources(device_t dev) |
| 418 | { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 419 | unsigned int reg; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 420 | |
| 421 | /* Find the already assigned resource pairs */ |
| 422 | get_fx_dev(); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 423 | for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 424 | u32 base, limit; |
| 425 | base = f1_read_config32(reg); |
| 426 | limit = f1_read_config32(reg + 0x04); |
| 427 | /* Is this register allocated? */ |
| 428 | if ((base & 3) != 0) { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 429 | unsigned int nodeid, reg_link; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 430 | device_t reg_dev; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 431 | if (reg < 0xc0) /* mmio */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 432 | nodeid = (limit & 0xf) + (base & 0x30); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 433 | else /* io */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 434 | nodeid = (limit & 0xf) + ((base >> 4) & 0x30); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 435 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 436 | reg_link = (limit >> 4) & 7; |
| 437 | reg_dev = __f0_dev; |
| 438 | if (reg_dev) { |
| 439 | /* Reserve the resource */ |
| 440 | struct resource *res; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 441 | res = new_resource(reg_dev, |
| 442 | IOINDEX(0x1000 + reg, |
| 443 | reg_link)); |
| 444 | if (res) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 445 | res->flags = 1; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 446 | } |
| 447 | } |
| 448 | } |
| 449 | /* FIXME: do we need to check extend conf space? |
| 450 | I don't believe that much preset value */ |
| 451 | |
| 452 | pci_domain_read_resources(dev); |
| 453 | } |
| 454 | |
| 455 | void domain_enable_resources(device_t dev) |
| 456 | { |
| 457 | if (acpi_is_wakeup_s3()) |
| 458 | AGESAWRAPPER(fchs3laterestore); |
| 459 | |
| 460 | /* Must be called after PCI enumeration and resource allocation */ |
| 461 | if (!acpi_is_wakeup_s3()) |
| 462 | AGESAWRAPPER(amdinitmid); |
| 463 | |
| 464 | printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); |
| 465 | } |
| 466 | |
| 467 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 468 | struct hw_mem_hole_info { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 469 | unsigned int hole_startk; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 470 | int node_id; |
| 471 | }; |
| 472 | |
| 473 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 474 | { |
| 475 | struct hw_mem_hole_info mem_hole; |
| 476 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 477 | mem_hole.node_id = -1; |
| 478 | dram_base_mask_t d; |
| 479 | u32 hole; |
| 480 | d = get_dram_base_mask(0); |
| 481 | hole = pci_read_config32(__f1_dev, 0xf0); |
| 482 | if (hole & 2) { |
| 483 | /* We found the hole */ |
| 484 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 485 | mem_hole.node_id = 0; /* record the node # with hole */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | return mem_hole; |
| 489 | } |
| 490 | #endif |
| 491 | |
| 492 | void domain_set_resources(device_t dev) |
| 493 | { |
| 494 | unsigned long mmio_basek; |
| 495 | u32 pci_tolm; |
| 496 | int i, idx; |
| 497 | struct bus *link; |
| 498 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 499 | struct hw_mem_hole_info mem_hole; |
| 500 | u32 reset_memhole = 1; |
| 501 | #endif |
| 502 | |
| 503 | pci_tolm = 0xffffffffUL; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 504 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 505 | pci_tolm = find_pci_tolm(link); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 506 | |
| 507 | mmio_basek = pci_tolm >> 10; |
| 508 | /* Round mmio_basek to something the processor can support */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 509 | mmio_basek &= ~((1 << 6) - 1); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 510 | |
| 511 | /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 512 | * MMIO hole. If you fix this here, please fix amdk8, too. |
| 513 | */ |
| 514 | /* Round the mmio hole to 64M */ |
| 515 | mmio_basek &= ~((64 * 1024) - 1); |
| 516 | |
| 517 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 518 | /* if the hw mem hole is already set in raminit stage, here we will |
| 519 | * compare mmio_basek and hole_basek. if mmio_basek is bigger that |
| 520 | * hole_basek and will use hole_basek as mmio_basek and we don't need |
| 521 | * to reset hole. Otherwise we reset the hole to the mmio_basek |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 522 | */ |
| 523 | |
| 524 | mem_hole = get_hw_mem_hole_info(); |
| 525 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 526 | /* Use hole_basek as mmio_basek, and no need to reset hole anymore */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 527 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 528 | mmio_basek = mem_hole.hole_startk; |
| 529 | reset_memhole = 0; |
| 530 | } |
| 531 | #endif |
| 532 | |
| 533 | idx = 0x10; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 534 | for (i = 0 ; i < node_nums ; i++) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 535 | dram_base_mask_t d; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 536 | resource_t basek, limitk, sizek; /* 4 1T */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 537 | |
| 538 | d = get_dram_base_mask(i); |
| 539 | |
| 540 | if (!(d.mask & 1)) |
| 541 | continue; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 542 | /* could overflow, we may lose 6 bit here */ |
| 543 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; |
| 544 | limitk = ((resource_t)(((d.mask & ~1) + 0x000ff) |
| 545 | & 0x1fffff00)) << 9; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 546 | |
| 547 | sizek = limitk - basek; |
| 548 | |
| 549 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 550 | if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) + |
| 551 | (16 * 16)))) { |
| 552 | ram_resource(dev, (idx | i), basek, |
| 553 | ((8 * 64) + (8 * 16)) - basek); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 554 | idx += 0x10; |
| 555 | basek = (8 * 64) + (16 * 16); |
| 556 | sizek = limitk - ((8 * 64) + (16 * 16)); |
| 557 | |
| 558 | } |
| 559 | |
| 560 | /* split the region to accommodate pci memory space */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 561 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 562 | if (basek <= mmio_basek) { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 563 | unsigned int pre_sizek; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 564 | pre_sizek = mmio_basek - basek; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 565 | if (pre_sizek > 0) { |
| 566 | ram_resource(dev, (idx | i), basek, |
| 567 | pre_sizek); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 568 | idx += 0x10; |
| 569 | sizek -= pre_sizek; |
| 570 | } |
| 571 | basek = mmio_basek; |
| 572 | } |
| 573 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
| 574 | sizek = 0; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 575 | } else { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 576 | uint64_t topmem2 = bsp_topmem2(); |
| 577 | basek = 4 * 1024 * 1024; |
| 578 | sizek = topmem2 / 1024 - basek; |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | ram_resource(dev, (idx | i), basek, sizek); |
| 583 | idx += 0x10; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 584 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx," |
| 585 | " limitk=%08llx\n", i, mmio_basek, basek, |
| 586 | limitk); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | add_uma_resource_below_tolm(dev, 7); |
| 590 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 591 | for (link = dev->link_list ; link ; link = link->next) |
| 592 | if (link->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 593 | assign_resources(link); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 594 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 595 | /* |
| 596 | * Reserve everything between A segment and 1MB: |
| 597 | * |
| 598 | * 0xa0000 - 0xbffff: legacy VGA |
| 599 | * 0xc0000 - 0xfffff: RAM |
| 600 | */ |
| 601 | mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB); |
| 602 | reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); |
| 603 | } |
| 604 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 605 | /* first node */ |
| 606 | static void sysconf_init(device_t dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 607 | { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 608 | /* don't forget sublink1 */ |
| 609 | sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; |
| 610 | /* NodeCnt[2:0] */ |
| 611 | node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 612 | } |
| 613 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 614 | void cpu_bus_scan(device_t dev) |
| 615 | { |
| 616 | struct bus *cpu_bus; |
| 617 | device_t cpu; |
| 618 | device_t cdb_dev; |
| 619 | device_t dev_mc; |
| 620 | int j; |
| 621 | int core_max; |
| 622 | int core_nums; |
| 623 | int siblings; |
| 624 | int family; |
| 625 | int enable_node; |
| 626 | u32 lapicid_start; |
| 627 | u32 apic_id; |
| 628 | u32 pccount; |
| 629 | |
| 630 | |
| 631 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 632 | if (!dev_mc) { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 633 | printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, |
| 634 | CONFIG_CDB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 635 | die(""); |
| 636 | } |
| 637 | sysconf_init(dev_mc); /* sets global node_nums */ |
| 638 | |
| 639 | if (node_nums != 1) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 640 | die("node_nums != 1. This is an SOC." |
| 641 | " Something is terribly wrong."); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 642 | |
| 643 | /* Get max and actual number of cores */ |
| 644 | pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 645 | core_max = 1 << ((pccount >> 12) & 0xf); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 646 | core_nums = (pccount & 0xF); |
| 647 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 648 | family = (cpuid_eax(1) >> 20) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 649 | |
| 650 | cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 651 | siblings = pci_read_config32(cdb_dev, 0x84) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 652 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 653 | printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d," |
| 654 | " siblings=%d\n", dev_path(cdb_dev), 0x0f + family, |
| 655 | core_max, core_nums, siblings); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 656 | |
| 657 | /* |
| 658 | * APIC ID calucation is tightly coupled with AGESA v5 code. |
| 659 | * This calculation MUST match the assignment calculation done |
| 660 | * in LocalApicInitializationAtEarly() function. |
| 661 | * And reference GetLocalApicIdForCore() |
| 662 | * |
| 663 | * Apply apic enumeration rules |
| 664 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 665 | * put the local-APICs at m..z |
| 666 | * |
| 667 | * This is needed because many IO-APIC devices only have 4 bits |
| 668 | * for their APIC id and therefore must reside at 0..15 |
| 669 | */ |
| 670 | |
| 671 | /* |
| 672 | * While the above statement is true, we know some things about |
| 673 | * this silicon. It is an SOC and can't have >= 16 APICs, but |
| 674 | * we will start numbering at 0x10. We also know there is only |
| 675 | * on physical node (module in AMD speak). |
| 676 | */ |
| 677 | |
| 678 | lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ |
| 679 | enable_node = cdb_dev && cdb_dev->enabled; |
| 680 | cpu_bus = dev->link_list; |
| 681 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 682 | for (j = 0 ; j <= siblings ; j++) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 683 | apic_id = lapicid_start + j; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 684 | printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x," |
| 685 | " apicid=0x%x\n", lapicid_start, node_nums, |
| 686 | j, apic_id); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 687 | |
| 688 | cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
| 689 | if (cpu) |
| 690 | amd_cpu_topology(cpu, node_nums, j); |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | /********************************************************************* |
| 695 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 696 | *********************************************************************/ |
| 697 | u32 map_oprom_vendev(u32 vendev) |
| 698 | { |
| 699 | u32 new_vendev; |
| 700 | new_vendev = |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 701 | ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? |
| 702 | 0x100298e0 : vendev; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 703 | |
| 704 | if (vendev != new_vendev) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame^] | 705 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", |
| 706 | vendev, new_vendev); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 707 | |
| 708 | return new_vendev; |
| 709 | } |