Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 2 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 3 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 4 | #include <console/console.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <device/device.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 9 | #include <boot/tables.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
Angel Pons | 2a8ceef | 2020-09-15 12:23:45 +0200 | [diff] [blame] | 11 | #include <northbridge/intel/x4x/memmap.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 12 | #include <northbridge/intel/x4x/chip.h> |
| 13 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 14 | #include <cpu/intel/smm_reloc.h> |
Arthur Heymans | 98c9257 | 2022-11-07 11:39:58 +0100 | [diff] [blame] | 15 | #include <cpu/intel/speedstep.h> |
Arthur Heymans | ca0436f | 2023-07-05 10:49:01 +0200 | [diff] [blame] | 16 | #include <cpu/x86/smm.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 17 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 18 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 19 | { |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 20 | u8 index; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | u64 tom, touud; |
Arthur Heymans | ca0436f | 2023-07-05 10:49:01 +0200 | [diff] [blame] | 22 | u32 tolud; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 23 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 24 | index = 3; |
| 25 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 26 | pci_domain_read_resources(dev); |
| 27 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 28 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 29 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 30 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 31 | touud = pci_read_config16(mch, D0F0_TOUUD); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 32 | touud <<= 20; |
| 33 | |
| 34 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 35 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 36 | tolud <<= 16; |
| 37 | |
| 38 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 39 | tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 40 | tom <<= 26; |
| 41 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 42 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 43 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 44 | /* Report the memory regions */ |
Kyösti Mälkki | 8ee11b3 | 2021-06-27 21:08:32 +0300 | [diff] [blame] | 45 | ram_from_to(dev, index++, 0, 0xa0000); |
| 46 | mmio_from_to(dev, index++, 0xa0000, 0xc0000); |
| 47 | reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); |
Arthur Heymans | ca0436f | 2023-07-05 10:49:01 +0200 | [diff] [blame] | 48 | ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 52 | * is remapped above TOM, TOUUD will account for both |
| 53 | */ |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 54 | upper_ram_end(dev, index++, touud); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 55 | |
Arthur Heymans | ca0436f | 2023-07-05 10:49:01 +0200 | [diff] [blame] | 56 | uintptr_t tseg_base; |
| 57 | size_t tseg_size; |
| 58 | smm_region(&tseg_base, &tseg_size); |
| 59 | mmio_from_to(dev, index++, tseg_base, tolud); |
| 60 | reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 61 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 62 | /* Reserve high memory where the NB BARs are up to 4GiB */ |
Arthur Heymans | ca0436f | 2023-07-05 10:49:01 +0200 | [diff] [blame] | 63 | mmio_from_to(dev, index++, DEFAULT_HECIBAR, 4ull * GiB); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 64 | |
Angel Pons | bbc80f4 | 2021-01-20 13:23:18 +0100 | [diff] [blame] | 65 | mmconf_resource(dev, index++); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 66 | } |
| 67 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 68 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 69 | { |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 70 | struct resource *res; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 71 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 72 | for (res = dev->resource_list; res; res = res->next) |
| 73 | report_resource_stored(dev, res, ""); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 74 | |
Arthur Heymans | 7fcd4d5 | 2023-08-24 15:12:19 +0200 | [diff] [blame] | 75 | assign_resources(dev->downstream); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 76 | } |
| 77 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 78 | static void mch_domain_init(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 79 | { |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 80 | /* Enable SERR */ |
Elyes HAOUAS | 5ac723e | 2020-04-29 09:09:12 +0200 | [diff] [blame] | 81 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 82 | } |
| 83 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 84 | static const char *northbridge_acpi_name(const struct device *dev) |
| 85 | { |
| 86 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 87 | return "PCI0"; |
| 88 | |
Fabio Aiuto | 61ed4ef | 2022-09-30 14:55:53 +0200 | [diff] [blame] | 89 | if (!is_pci_dev_on_bus(dev, 0)) |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 90 | return NULL; |
| 91 | |
| 92 | switch (dev->path.pci.devfn) { |
| 93 | case PCI_DEVFN(0, 0): |
| 94 | return "MCHC"; |
| 95 | } |
| 96 | |
| 97 | return NULL; |
| 98 | } |
| 99 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 100 | void northbridge_write_smram(u8 smram) |
| 101 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 102 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 103 | |
Elyes Haouas | 5e6b0f0 | 2022-09-13 09:55:49 +0200 | [diff] [blame] | 104 | if (!dev) |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 105 | die("could not find pci 00:00.0!\n"); |
| 106 | |
| 107 | pci_write_config8(dev, D0F0_SMRAM, smram); |
| 108 | } |
| 109 | |
Arthur Heymans | 1eecb8c | 2022-11-07 10:04:56 +0100 | [diff] [blame] | 110 | struct device_operations x4x_pci_domain_ops = { |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 111 | .read_resources = mch_domain_read_resources, |
| 112 | .set_resources = mch_domain_set_resources, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 113 | .init = mch_domain_init, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 114 | .scan_bus = pci_host_bridge_scan_bus, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 115 | .write_acpi_tables = northbridge_write_acpi_tables, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 116 | .acpi_fill_ssdt = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 117 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 118 | }; |
| 119 | |
Arthur Heymans | 1eecb8c | 2022-11-07 10:04:56 +0100 | [diff] [blame] | 120 | struct device_operations x4x_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 121 | .read_resources = noop_read_resources, |
| 122 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 123 | .init = mp_cpu_bus_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 124 | }; |
| 125 | |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 126 | static void hide_pci_fn(const int dev_bit_base, const struct device *dev) |
| 127 | { |
| 128 | if (!dev || dev->enabled) |
| 129 | return; |
| 130 | const unsigned int fn = PCI_FUNC(dev->path.pci.devfn); |
| 131 | const struct device *const d0f0 = pcidev_on_root(0, 0); |
| 132 | pci_update_config32(d0f0, D0F0_DEVEN, ~(1 << (dev_bit_base + fn)), 0); |
| 133 | } |
| 134 | |
| 135 | static void hide_pci_dev(const int dev, int functions, const int dev_bit_base) |
| 136 | { |
| 137 | for (; functions >= 0; functions--) |
| 138 | hide_pci_fn(dev_bit_base, pcidev_on_root(dev, functions)); |
| 139 | } |
| 140 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 141 | static void x4x_init(void *const chip_info) |
| 142 | { |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 143 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 144 | |
| 145 | /* Hide internal functions based on devicetree info. */ |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 146 | hide_pci_dev(6, 0, 13); /* PEG1: only on P45 */ |
| 147 | hide_pci_dev(3, 3, 6); /* ME */ |
| 148 | hide_pci_dev(2, 1, 3); /* IGD */ |
| 149 | hide_pci_dev(1, 0, 1); /* PEG0 */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 150 | |
| 151 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 152 | if (!(deven & (0xf << 6))) |
| 153 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 154 | } |
| 155 | |
| 156 | struct chip_operations northbridge_intel_x4x_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame] | 157 | .name = "Intel 4-Series Northbridge", |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 158 | .init = x4x_init, |
| 159 | }; |
Arthur Heymans | 98c9257 | 2022-11-07 11:39:58 +0100 | [diff] [blame] | 160 | |
| 161 | bool northbridge_support_slfm(void) |
| 162 | { |
| 163 | return false; |
| 164 | } |