Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Apollolake support |
| 5 | |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 6 | config SOC_INTEL_GEMINILAKE |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 7 | bool |
| 8 | default n |
| 9 | select SOC_INTEL_APOLLOLAKE |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 10 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 11 | select SOC_INTEL_COMMON_BLOCK_SGX |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 12 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Aaron Durbin | 82d0f91 | 2018-04-21 00:16:28 -0600 | [diff] [blame] | 13 | select IDT_IN_EVERY_STAGE |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 14 | select PAGING_IN_CACHE_AS_RAM |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 15 | help |
| 16 | Intel GLK support |
| 17 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 18 | if SOC_INTEL_APOLLOLAKE |
| 19 | |
| 20 | config CPU_SPECIFIC_OPTIONS |
| 21 | def_bool y |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 22 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Nico Huber | 44c6cf6 | 2018-11-24 17:53:17 +0100 | [diff] [blame] | 23 | select ACPI_NO_PCAT_8259 |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 24 | select ARCH_ALL_STAGES_X86_32 |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 25 | select BOOT_DEVICE_SUPPORTS_WRITES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 26 | # CPU specific options |
Angel Pons | ae0d8d6 | 2020-09-02 15:00:40 +0200 | [diff] [blame] | 27 | select CPU_INTEL_COMMON |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 28 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 29 | select IOAPIC |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 30 | select PCR_COMMON_IOSF_1_0 |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 31 | select SSE2 |
| 32 | select SUPPORT_CPU_UCODE_IN_CBFS |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 33 | # Audio options |
| 34 | select ACPI_NHLT |
| 35 | select SOC_INTEL_COMMON_NHLT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 36 | # Misc options |
Aaron Durbin | 934f433 | 2017-12-15 12:59:18 -0700 | [diff] [blame] | 37 | select CACHE_MRC_SETTINGS |
Ravi Sarawadi | a3d13fbd6 | 2017-04-25 19:30:58 -0700 | [diff] [blame] | 38 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 39 | select GENERIC_GPIO_LIB |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 40 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 41 | select HAVE_SMI_HANDLER |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 42 | select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE |
Furquan Shaikh | ffb3a2d | 2016-10-24 15:28:23 -0700 | [diff] [blame] | 43 | select MRC_SETTINGS_PROTECT |
Aaron Durbin | 934f433 | 2017-12-15 12:59:18 -0700 | [diff] [blame] | 44 | select MRC_SETTINGS_VARIABLE_DATA |
Furquan Shaikh | 94b18a1 | 2016-05-04 23:25:16 -0700 | [diff] [blame] | 45 | select NO_XIP_EARLY_STAGES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 46 | select PARALLEL_MP |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 47 | select PARALLEL_MP_AP_WORK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 48 | select PCIEXP_ASPM |
| 49 | select PCIEXP_COMMON_CLOCK |
| 50 | select PCIEXP_CLK_PM |
| 51 | select PCIEXP_L1_SUB_STATE |
Hannah Williams | 1177bf5 | 2017-12-13 12:44:26 -0800 | [diff] [blame] | 52 | select PMC_INVALID_READ_AFTER_WRITE |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 53 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 54 | select REG_SCRIPT |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 55 | select SA_ENABLE_IMR |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_CPU |
Lijian Zhao | 44e2abf | 2017-10-30 14:27:52 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_DSP |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Hannah Williams | 12bed18 | 2017-05-26 20:31:15 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_GPIO |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Aaron Durbin | aa2504a | 2017-07-14 16:53:49 -0600 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES |
Hannah Williams | 12bed18 | 2017-05-26 20:31:15 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG |
| 69 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | b7b5666 | 2017-11-28 17:54:15 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_GRAPHICS |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_ITSS |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_I2C |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_LPC |
Aamir Bohra | 138b2a0 | 2017-04-06 20:21:58 +0530 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_BLOCK_LPSS |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_PCR |
Lijian Zhao | 8aba24d | 2017-10-26 12:16:53 -0700 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK_P2SB |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_BLOCK_PMC |
V Sowmya | 45a2138 | 2017-11-27 12:39:10 +0530 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK_SRAM |
Subrata Banik | 8bf69d3 | 2017-03-09 13:43:54 +0530 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_RTC |
Aamir Bohra | bf6dfae | 2017-04-07 21:10:27 +0530 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_SA |
Bora Guvendik | 65623b7 | 2017-05-08 16:29:17 -0700 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK_SCS |
Aamir Bohra | 4c9cf30 | 2017-05-25 14:38:37 +0530 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_BLOCK_TIMER |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_BLOCK_TCO |
Aamir Bohra | bf6dfae | 2017-04-07 21:10:27 +0530 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_BLOCK_UART |
Subrata Banik | 4aaa7e3 | 2017-04-24 11:54:34 +0530 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_XDCI |
Subrata Banik | 73b1797 | 2017-04-24 10:25:56 +0530 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK_XHCI |
Karthikeyan Ramasubramanian | f84c103 | 2019-03-20 13:15:00 -0600 | [diff] [blame] | 87 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK_SMM |
Subrata Banik | 15129b4 | 2017-11-07 17:50:48 +0530 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_SPI |
Marshall Dawson | 0cc28d7 | 2017-12-12 12:24:19 -0700 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_CSE |
Maxim Polyakov | 0c5dd9f | 2020-08-14 19:24:12 +0300 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_SMBUS |
| 92 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 93 | select UDELAY_TSC |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 94 | select TSC_MONOTONIC_TIMER |
Andrey Petrov | 0d18791 | 2016-02-25 18:39:38 -0800 | [diff] [blame] | 95 | select PLATFORM_USES_FSP2_0 |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 96 | select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE |
| 97 | select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 98 | select SOC_INTEL_COMMON_RESET |
Furquan Shaikh | b13bd1e | 2020-09-21 22:44:27 +0000 | [diff] [blame] | 99 | select HAVE_CF9_RESET_PREPARE |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 100 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Nico Huber | 2e7f6cc | 2017-05-22 15:58:03 +0200 | [diff] [blame] | 101 | select HAVE_FSP_GOP |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 102 | select HAVE_FSP_LOGO_SUPPORT |
Ravi Sarawadi | 92b487d | 2017-11-29 16:11:32 -0800 | [diff] [blame] | 103 | select NO_UART_ON_SUPERIO |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 104 | select INTEL_GMA_ACPI |
| 105 | select INTEL_GMA_SWSMISCI |
Harshit Sharma | 7fe5ea4 | 2020-08-03 23:25:36 -0700 | [diff] [blame] | 106 | select HAVE_ASAN_IN_ROMSTAGE |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 107 | |
Angel Pons | f4779e8 | 2020-09-07 13:40:47 +0200 | [diff] [blame] | 108 | config MAX_CPUS |
| 109 | int |
Angel Pons | c6c9b9c | 2020-09-07 13:45:53 +0200 | [diff] [blame] | 110 | default 4 |
Angel Pons | f4779e8 | 2020-09-07 13:40:47 +0200 | [diff] [blame] | 111 | |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 112 | config CHROMEOS |
| 113 | select CHROMEOS_RAMOOPS_DYNAMIC |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 114 | |
| 115 | config VBOOT |
| 116 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 117 | select VBOOT_MUST_REQUEST_DISPLAY |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 118 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 119 | select VBOOT_VBNV_CMOS |
| 120 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 121 | |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 122 | config TPM_ON_FAST_SPI |
| 123 | bool |
| 124 | default n |
Philipp Deppenwiese | c07f8fb | 2018-02-27 19:40:52 +0100 | [diff] [blame] | 125 | depends on MAINBOARD_HAS_LPC_TPM |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 126 | help |
| 127 | TPM part is conntected on Fast SPI interface, but the LPC MMIO |
| 128 | TPM transactions are decoded and serialized over the SPI interface. |
| 129 | |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 130 | config PCR_BASE_ADDRESS |
| 131 | hex |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 132 | default 0xd0000000 |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 133 | help |
| 134 | This option allows you to select MMIO Base Address of sideband bus. |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 135 | |
| 136 | config DCACHE_RAM_BASE |
Arthur Heymans | 3038b48 | 2017-06-13 14:05:09 +0200 | [diff] [blame] | 137 | hex |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 138 | default 0xfef00000 |
| 139 | |
| 140 | config DCACHE_RAM_SIZE |
Arthur Heymans | 3038b48 | 2017-06-13 14:05:09 +0200 | [diff] [blame] | 141 | hex |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 142 | default 0x100000 if SOC_INTEL_GEMINILAKE |
Andrey Petrov | 0dde291 | 2016-06-27 15:21:26 -0700 | [diff] [blame] | 143 | default 0xc0000 |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 144 | help |
| 145 | The size of the cache-as-ram region required during bootblock |
| 146 | and/or romstage. |
| 147 | |
| 148 | config DCACHE_BSP_STACK_SIZE |
| 149 | hex |
| 150 | default 0x4000 |
| 151 | help |
| 152 | The amount of anticipated stack usage in CAR by bootblock and |
| 153 | other stages. |
| 154 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 155 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 156 | int |
Aaron Durbin | 24de597 | 2018-04-10 09:28:42 -0600 | [diff] [blame] | 157 | default 100 |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 158 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 159 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 160 | int |
Aaron Durbin | 24de597 | 2018-04-10 09:28:42 -0600 | [diff] [blame] | 161 | default 133 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 162 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 163 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 164 | config C_ENV_BOOTBLOCK_SIZE |
| 165 | hex |
| 166 | default 0x8000 |
| 167 | |
Andrey Petrov | 5672dcd | 2016-02-12 15:12:43 -0800 | [diff] [blame] | 168 | # This SoC does not map SPI flash like many previous SoC. Therefore we provide |
| 169 | # a custom media driver that facilitates mapping |
| 170 | config X86_TOP4G_BOOTMEDIA_MAP |
| 171 | bool |
| 172 | default n |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 173 | |
| 174 | config ROMSTAGE_ADDR |
| 175 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 176 | default 0xfef20000 |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 177 | help |
| 178 | The base address (in CAR) where romstage should be linked |
| 179 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 180 | config VERSTAGE_ADDR |
| 181 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 182 | default 0xfef40000 |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 183 | help |
| 184 | The base address (in CAR) where verstage should be linked |
| 185 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 186 | config FSP_HEADER_PATH |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 187 | default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 188 | default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" |
| 189 | |
| 190 | config FSP_FD_PATH |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 191 | default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" |
| 192 | |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 193 | config FSP_M_ADDR |
| 194 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 195 | default 0xfef40000 |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 196 | help |
| 197 | The address FSP-M will be relocated to during build time |
| 198 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 199 | config NEED_LBP2 |
| 200 | bool "Write contents for logical boot partition 2." |
| 201 | default n |
| 202 | help |
| 203 | Write the contents from a file into the logical boot partition 2 |
| 204 | region defined by LBP2_FMAP_NAME. |
| 205 | |
| 206 | config LBP2_FMAP_NAME |
| 207 | string "Name of FMAP region to put logical boot partition 2" |
| 208 | depends on NEED_LBP2 |
| 209 | default "SIGN_CSE" |
| 210 | help |
| 211 | Name of FMAP region to write logical boot partition 2 data. |
| 212 | |
Jeremy Compostella | 0f9858f | 2019-12-12 14:39:11 -0700 | [diff] [blame] | 213 | config LBP2_FROM_IFWI |
| 214 | bool "Extract the LBP2 from the IFWI binary" |
| 215 | depends on NEED_LBP2 |
| 216 | default n |
| 217 | help |
| 218 | The Logical Boot Partition will be automatically extracted |
| 219 | from the supplied IFWI binary |
| 220 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 221 | config LBP2_FILE_NAME |
| 222 | string "Path of file to write to logical boot partition 2 region" |
Jeremy Compostella | 0f9858f | 2019-12-12 14:39:11 -0700 | [diff] [blame] | 223 | depends on NEED_LBP2 && !LBP2_FROM_IFWI |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 224 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/lbp2.bin" |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 225 | help |
| 226 | Name of file to store in the logical boot partition 2 region. |
| 227 | |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 228 | config NEED_IFWI |
| 229 | bool "Write content into IFWI region" |
| 230 | default n |
| 231 | help |
| 232 | Write the content from a file into IFWI region defined by |
| 233 | IFWI_FMAP_NAME. |
| 234 | |
| 235 | config IFWI_FMAP_NAME |
| 236 | string "Name of FMAP region to pull IFWI into" |
| 237 | depends on NEED_IFWI |
| 238 | default "IFWI" |
| 239 | help |
| 240 | Name of FMAP region to write IFWI. |
| 241 | |
| 242 | config IFWI_FILE_NAME |
| 243 | string "Path of file to write to IFWI region" |
| 244 | depends on NEED_IFWI |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 245 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/ifwi.bin" |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 246 | help |
| 247 | Name of file to store in the IFWI region. |
| 248 | |
Sathyanarayana Nujella | c446704 | 2016-10-26 17:38:49 -0700 | [diff] [blame] | 249 | config HEAP_SIZE |
| 250 | hex |
| 251 | default 0x8000 |
| 252 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 253 | config NHLT_DMIC_1CH_16B |
| 254 | bool |
| 255 | depends on ACPI_NHLT |
| 256 | default n |
| 257 | help |
| 258 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 259 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 260 | config NHLT_DMIC_2CH_16B |
| 261 | bool |
| 262 | depends on ACPI_NHLT |
| 263 | default n |
| 264 | help |
| 265 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 266 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 267 | config NHLT_DMIC_4CH_16B |
| 268 | bool |
| 269 | depends on ACPI_NHLT |
| 270 | default n |
| 271 | help |
| 272 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 273 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 274 | config NHLT_MAX98357 |
| 275 | bool |
| 276 | depends on ACPI_NHLT |
| 277 | default n |
| 278 | help |
| 279 | Include DSP firmware settings for headset codec. |
| 280 | |
| 281 | config NHLT_DA7219 |
| 282 | bool |
| 283 | depends on ACPI_NHLT |
| 284 | default n |
| 285 | help |
| 286 | Include DSP firmware settings for headset codec. |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 287 | |
Naveen Manohar | 532b8d5 | 2018-04-27 15:24:45 +0530 | [diff] [blame] | 288 | config NHLT_RT5682 |
| 289 | bool |
| 290 | depends on ACPI_NHLT |
| 291 | default n |
| 292 | help |
| 293 | Include DSP firmware settings for headset codec. |
| 294 | |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 295 | choice |
| 296 | prompt "Cache-as-ram implementation" |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 297 | default CAR_CQOS if !SOC_INTEL_GEMINILAKE |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 298 | default CAR_NEM |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 299 | help |
| 300 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 301 | |
| 302 | config CAR_NEM |
| 303 | bool "Non-evict mode" |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 304 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 305 | select INTEL_CAR_NEM |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 306 | help |
| 307 | Traditionally, CAR is set up by using Non-Evict mode. This method |
| 308 | does not allow CAR and cache to co-exist, because cache fills are |
| 309 | block in NEM mode. |
| 310 | |
| 311 | config CAR_CQOS |
| 312 | bool "Cache Quality of Service" |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 313 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 314 | select INTEL_CAR_CQOS |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 315 | help |
| 316 | Cache Quality of Service allows more fine-grained control of cache |
| 317 | usage. As result, it is possible to set up portion of L2 cache for |
| 318 | CAR and use remainder for actual caching. |
| 319 | |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 320 | config USE_APOLLOLAKE_FSP_CAR |
| 321 | bool "Use FSP CAR" |
| 322 | select FSP_CAR |
| 323 | help |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 324 | Use FSP APIs to initialize & tear down the Cache-As-Ram. |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 325 | |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 326 | endchoice |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 327 | |
Subrata Banik | 8e1c12f1 | 2017-03-10 13:51:11 +0530 | [diff] [blame] | 328 | # |
| 329 | # Each bit in QOS mask controls this many bytes. This is calculated as: |
| 330 | # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS |
| 331 | # |
| 332 | |
| 333 | config CACHE_QOS_SIZE_PER_BIT |
| 334 | hex |
| 335 | default 0x20000 # 128 KB |
| 336 | |
| 337 | config L2_CACHE_SIZE |
| 338 | hex |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 339 | default 0x400000 if SOC_INTEL_GEMINILAKE |
Subrata Banik | 8e1c12f1 | 2017-03-10 13:51:11 +0530 | [diff] [blame] | 340 | default 0x100000 |
| 341 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 342 | config SMM_RESERVED_SIZE |
| 343 | hex |
| 344 | default 0x100000 |
| 345 | |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 346 | config IFD_CHIPSET |
| 347 | string |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 348 | default "glk" if SOC_INTEL_GEMINILAKE |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 349 | default "aplk" |
| 350 | |
Aamir Bohra | 22b2c79 | 2017-06-02 19:07:56 +0530 | [diff] [blame] | 351 | config CPU_BCLK_MHZ |
| 352 | int |
| 353 | default 100 |
| 354 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 355 | config CONSOLE_UART_BASE_ADDRESS |
| 356 | hex |
| 357 | default 0xddffc000 |
| 358 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 359 | |
Mario Scheithauer | 38b6100 | 2017-07-25 10:52:41 +0200 | [diff] [blame] | 360 | config APL_SKIP_SET_POWER_LIMITS |
| 361 | bool |
| 362 | default n |
| 363 | help |
| 364 | Some Apollo Lake mainboards do not need the Running Average Power |
| 365 | Limits (RAPL) algorithm for a constant power management. |
| 366 | Set this config option to skip the RAPL configuration. |
| 367 | |
Werner Zeh | 2636186 | 2018-11-21 12:36:21 +0100 | [diff] [blame] | 368 | config APL_SET_MIN_CLOCK_RATIO |
| 369 | bool |
| 370 | depends on !APL_SKIP_SET_POWER_LIMITS |
| 371 | default n |
| 372 | help |
| 373 | If the power budget of the mainboard is limited, it can be useful to |
| 374 | limit the CPU power dissipation at the cost of performance by setting |
| 375 | the lowest possible CPU clock. Enable this option if you need smallest |
| 376 | possible CPU clock. This setting can be overruled by the OS if it has an |
| 377 | p-state driver which can adjust the clock to its need. |
| 378 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 379 | # M and N divisor values for clock frequency configuration. |
| 380 | # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) |
| 381 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 382 | hex |
| 383 | default 0x25a |
| 384 | |
| 385 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 386 | hex |
| 387 | default 0x7fff |
| 388 | |
Bora Guvendik | 94aed8d | 2017-11-03 12:40:25 -0700 | [diff] [blame] | 389 | config SOC_ESPI |
| 390 | bool |
| 391 | default n |
| 392 | help |
| 393 | Use eSPI bus instead of LPC |
| 394 | |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 395 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 396 | int |
| 397 | default 3 |
| 398 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 399 | config SOC_INTEL_I2C_DEV_MAX |
| 400 | int |
| 401 | default 8 |
| 402 | |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 403 | # Don't include the early page tables in RW_A or RW_B cbfs regions |
| 404 | config RO_REGION_ONLY |
| 405 | string |
| 406 | default "pdpt pt" |
| 407 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 408 | endif |