Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Apollolake support |
| 5 | |
| 6 | if SOC_INTEL_APOLLOLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
Aaron Durbin | a9e03a3 | 2016-09-16 19:25:43 -0500 | [diff] [blame] | 15 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | 7b2c781 | 2016-08-11 23:51:42 -0500 | [diff] [blame] | 16 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 18 | # CPU specific options |
| 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 20 | select IOAPIC |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 21 | select PCR_COMMON_IOSF_1_0 |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 22 | select SMP |
| 23 | select SSE2 |
| 24 | select SUPPORT_CPU_UCODE_IN_CBFS |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 25 | # Audio options |
| 26 | select ACPI_NHLT |
| 27 | select SOC_INTEL_COMMON_NHLT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 28 | # Misc options |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 29 | select C_ENVIRONMENT_BOOTBLOCK |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 30 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 31 | select COLLECT_TIMESTAMPS |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 32 | select COMMON_FADT |
Ravi Sarawadi | a3d13fbd6 | 2017-04-25 19:30:58 -0700 | [diff] [blame] | 33 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 34 | select GENERIC_GPIO_LIB |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 35 | select HAVE_INTEL_FIRMWARE |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 36 | select HAVE_SMI_HANDLER |
Furquan Shaikh | ffb3a2d | 2016-10-24 15:28:23 -0700 | [diff] [blame] | 37 | select MRC_SETTINGS_PROTECT |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 38 | select NO_FIXED_XIP_ROM_SIZE |
Furquan Shaikh | 94b18a1 | 2016-05-04 23:25:16 -0700 | [diff] [blame] | 39 | select NO_XIP_EARLY_STAGES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 40 | select PARALLEL_MP |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 41 | select PARALLEL_MP_AP_WORK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 42 | select PCIEXP_ASPM |
| 43 | select PCIEXP_COMMON_CLOCK |
| 44 | select PCIEXP_CLK_PM |
| 45 | select PCIEXP_L1_SUB_STATE |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 46 | select PCIEX_LENGTH_256MB |
Aaron Durbin | 79587ed | 2016-09-16 16:30:09 -0500 | [diff] [blame] | 47 | select POSTCAR_CONSOLE |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 48 | select POSTCAR_STAGE |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 49 | select REG_SCRIPT |
| 50 | select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 51 | select RTC |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 52 | select SMM_TSEG |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_ACPI |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame^] | 57 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_ITSS |
Aamir Bohra | 138b2a0 | 2017-04-06 20:21:58 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_LPSS |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_PCR |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 8bf69d3 | 2017-03-09 13:43:54 +0530 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_RTC |
Aamir Bohra | bf6dfae | 2017-04-07 21:10:27 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_SA |
| 64 | select SOC_INTEL_COMMON_BLOCK_UART |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_LPSS_I2C |
| 66 | select SOC_INTEL_COMMON_SMI |
Furquan Shaikh | d0c00052 | 2016-11-21 09:19:53 -0800 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_SPI_FLASH_PROTECT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 68 | select UDELAY_TSC |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 69 | select TSC_CONSTANT_RATE |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 70 | select TSC_MONOTONIC_TIMER |
| 71 | select HAVE_MONOTONIC_TIMER |
Andrey Petrov | 0d18791 | 2016-02-25 18:39:38 -0800 | [diff] [blame] | 72 | select PLATFORM_USES_FSP2_0 |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 73 | select HAVE_HARD_RESET |
| 74 | select SOC_INTEL_COMMON |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_GFX_OPREGION |
Andrey Petrov | d8db26d | 2017-03-06 14:47:05 -0800 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK |
| 77 | select SOC_INTEL_COMMON_BLOCK_CSE |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 78 | select ADD_VBT_DATA_FILE |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 79 | |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 80 | config CHROMEOS |
| 81 | select CHROMEOS_RAMOOPS_DYNAMIC |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 82 | |
| 83 | config VBOOT |
| 84 | select VBOOT_SEPARATE_VERSTAGE |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 85 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | 7c7b291 | 2016-07-22 09:02:35 -0700 | [diff] [blame] | 86 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 87 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 88 | select VBOOT_VBNV_CMOS |
| 89 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 90 | |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 91 | config TPM_ON_FAST_SPI |
| 92 | bool |
| 93 | default n |
| 94 | select LPC_TPM |
| 95 | help |
| 96 | TPM part is conntected on Fast SPI interface, but the LPC MMIO |
| 97 | TPM transactions are decoded and serialized over the SPI interface. |
| 98 | |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 99 | config SOC_INTEL_COMMON_RESET |
| 100 | bool |
Andrey Petrov | 9c0e180 | 2016-06-23 08:26:00 -0700 | [diff] [blame] | 101 | default y |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 102 | |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 103 | config PCR_BASE_ADDRESS |
| 104 | hex |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 105 | default 0xd0000000 |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 106 | help |
| 107 | This option allows you to select MMIO Base Address of sideband bus. |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 108 | |
| 109 | config DCACHE_RAM_BASE |
| 110 | hex "Base address of cache-as-RAM" |
| 111 | default 0xfef00000 |
| 112 | |
| 113 | config DCACHE_RAM_SIZE |
| 114 | hex "Length in bytes of cache-as-RAM" |
Andrey Petrov | 0dde291 | 2016-06-27 15:21:26 -0700 | [diff] [blame] | 115 | default 0xc0000 |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 116 | help |
| 117 | The size of the cache-as-ram region required during bootblock |
| 118 | and/or romstage. |
| 119 | |
| 120 | config DCACHE_BSP_STACK_SIZE |
| 121 | hex |
| 122 | default 0x4000 |
| 123 | help |
| 124 | The amount of anticipated stack usage in CAR by bootblock and |
| 125 | other stages. |
| 126 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 127 | config CPU_ADDR_BITS |
| 128 | int |
| 129 | default 36 |
| 130 | |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 131 | config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 132 | int |
| 133 | default 133 |
| 134 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 135 | config CONSOLE_UART_BASE_ADDRESS |
| 136 | depends on CONSOLE_SERIAL |
| 137 | hex "MMIO base address for UART" |
| 138 | default 0xde000000 |
| 139 | |
Aaron Durbin | 6181030 | 2016-02-24 18:49:07 -0600 | [diff] [blame] | 140 | config SOC_UART_DEBUG |
| 141 | bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." |
| 142 | default n |
| 143 | select CONSOLE_SERIAL |
Aaron Durbin | 6181030 | 2016-02-24 18:49:07 -0600 | [diff] [blame] | 144 | select DRIVERS_UART |
| 145 | select DRIVERS_UART_8250MEM_32 |
| 146 | select NO_UART_ON_SUPERIO |
| 147 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 148 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 149 | config C_ENV_BOOTBLOCK_SIZE |
| 150 | hex |
| 151 | default 0x8000 |
| 152 | |
Andrey Petrov | 5672dcd | 2016-02-12 15:12:43 -0800 | [diff] [blame] | 153 | # This SoC does not map SPI flash like many previous SoC. Therefore we provide |
| 154 | # a custom media driver that facilitates mapping |
| 155 | config X86_TOP4G_BOOTMEDIA_MAP |
| 156 | bool |
| 157 | default n |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 158 | |
| 159 | config ROMSTAGE_ADDR |
| 160 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 161 | default 0xfef20000 |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 162 | help |
| 163 | The base address (in CAR) where romstage should be linked |
| 164 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 165 | config VERSTAGE_ADDR |
| 166 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 167 | default 0xfef40000 |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 168 | help |
| 169 | The base address (in CAR) where verstage should be linked |
| 170 | |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 171 | config CACHE_MRC_SETTINGS |
| 172 | bool |
| 173 | default y |
| 174 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 175 | config MRC_SETTINGS_VARIABLE_DATA |
| 176 | bool |
| 177 | default y |
| 178 | |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 179 | config FSP_M_ADDR |
| 180 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 181 | default 0xfef40000 |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 182 | help |
| 183 | The address FSP-M will be relocated to during build time |
| 184 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 185 | config NEED_LBP2 |
| 186 | bool "Write contents for logical boot partition 2." |
| 187 | default n |
| 188 | help |
| 189 | Write the contents from a file into the logical boot partition 2 |
| 190 | region defined by LBP2_FMAP_NAME. |
| 191 | |
| 192 | config LBP2_FMAP_NAME |
| 193 | string "Name of FMAP region to put logical boot partition 2" |
| 194 | depends on NEED_LBP2 |
| 195 | default "SIGN_CSE" |
| 196 | help |
| 197 | Name of FMAP region to write logical boot partition 2 data. |
| 198 | |
| 199 | config LBP2_FILE_NAME |
| 200 | string "Path of file to write to logical boot partition 2 region" |
| 201 | depends on NEED_LBP2 |
| 202 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" |
| 203 | help |
| 204 | Name of file to store in the logical boot partition 2 region. |
| 205 | |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 206 | config NEED_IFWI |
| 207 | bool "Write content into IFWI region" |
| 208 | default n |
| 209 | help |
| 210 | Write the content from a file into IFWI region defined by |
| 211 | IFWI_FMAP_NAME. |
| 212 | |
| 213 | config IFWI_FMAP_NAME |
| 214 | string "Name of FMAP region to pull IFWI into" |
| 215 | depends on NEED_IFWI |
| 216 | default "IFWI" |
| 217 | help |
| 218 | Name of FMAP region to write IFWI. |
| 219 | |
| 220 | config IFWI_FILE_NAME |
| 221 | string "Path of file to write to IFWI region" |
| 222 | depends on NEED_IFWI |
| 223 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" |
| 224 | help |
| 225 | Name of file to store in the IFWI region. |
| 226 | |
Sathyanarayana Nujella | c446704 | 2016-10-26 17:38:49 -0700 | [diff] [blame] | 227 | config HEAP_SIZE |
| 228 | hex |
| 229 | default 0x8000 |
| 230 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 231 | config NHLT_DMIC_1CH_16B |
| 232 | bool |
| 233 | depends on ACPI_NHLT |
| 234 | default n |
| 235 | help |
| 236 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 237 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 238 | config NHLT_DMIC_2CH_16B |
| 239 | bool |
| 240 | depends on ACPI_NHLT |
| 241 | default n |
| 242 | help |
| 243 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 244 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 245 | config NHLT_DMIC_4CH_16B |
| 246 | bool |
| 247 | depends on ACPI_NHLT |
| 248 | default n |
| 249 | help |
| 250 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 251 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 252 | config NHLT_MAX98357 |
| 253 | bool |
| 254 | depends on ACPI_NHLT |
| 255 | default n |
| 256 | help |
| 257 | Include DSP firmware settings for headset codec. |
| 258 | |
| 259 | config NHLT_DA7219 |
| 260 | bool |
| 261 | depends on ACPI_NHLT |
| 262 | default n |
| 263 | help |
| 264 | Include DSP firmware settings for headset codec. |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 265 | |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 266 | choice |
| 267 | prompt "Cache-as-ram implementation" |
| 268 | default CAR_CQOS |
| 269 | help |
| 270 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 271 | |
| 272 | config CAR_NEM |
| 273 | bool "Non-evict mode" |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 274 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 275 | select INTEL_CAR_NEM |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 276 | help |
| 277 | Traditionally, CAR is set up by using Non-Evict mode. This method |
| 278 | does not allow CAR and cache to co-exist, because cache fills are |
| 279 | block in NEM mode. |
| 280 | |
| 281 | config CAR_CQOS |
| 282 | bool "Cache Quality of Service" |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 283 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 284 | select INTEL_CAR_CQOS |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 285 | help |
| 286 | Cache Quality of Service allows more fine-grained control of cache |
| 287 | usage. As result, it is possible to set up portion of L2 cache for |
| 288 | CAR and use remainder for actual caching. |
| 289 | |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 290 | config USE_APOLLOLAKE_FSP_CAR |
| 291 | bool "Use FSP CAR" |
| 292 | select FSP_CAR |
| 293 | help |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 294 | Use FSP APIs to initialize & tear down the Cache-As-Ram. |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 295 | |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 296 | endchoice |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 297 | |
Subrata Banik | 8e1c12f1 | 2017-03-10 13:51:11 +0530 | [diff] [blame] | 298 | # |
| 299 | # Each bit in QOS mask controls this many bytes. This is calculated as: |
| 300 | # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS |
| 301 | # |
| 302 | |
| 303 | config CACHE_QOS_SIZE_PER_BIT |
| 304 | hex |
| 305 | default 0x20000 # 128 KB |
| 306 | |
| 307 | config L2_CACHE_SIZE |
| 308 | hex |
| 309 | default 0x100000 |
| 310 | |
Aaron Durbin | bdb6cc9 | 2016-08-11 09:48:52 -0500 | [diff] [blame] | 311 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
| 312 | bool |
| 313 | default n |
| 314 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 315 | config SMM_RESERVED_SIZE |
| 316 | hex |
| 317 | default 0x100000 |
| 318 | |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 319 | config IFD_CHIPSET |
| 320 | string |
| 321 | default "aplk" |
| 322 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 323 | endif |