soc/apollolake: Add initial cache-as-ram setup for bootblock
This is the minimum setup needed to both get cache-as-ram setup and a
C environment working. On apollolake, we only get 32 KiB of data
loaded into an SRAM that is readonly to the main CPU. Due to this
restriction we have to set CAR and a C environment very early on.
Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index ca38494..e39fc9c 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -18,6 +18,7 @@
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
# Misc options
+ select C_ENVIRONMENT_BOOTBLOCK
select COLLECT_TIMESTAMPS
select HAVE_INTEL_FIRMWARE
select MMCONF_SUPPORT
@@ -32,6 +33,32 @@
select SOC_INTEL_COMMON
select UDELAY_TSC
+config MMCONF_BASE_ADDRESS
+ hex "PCI MMIO Base Address"
+ default 0xe0000000
+
+config IOSF_BASE_ADDRESS
+ hex "MMIO Base Address of sideband bus"
+ default 0xd0000000
+
+config DCACHE_RAM_BASE
+ hex "Base address of cache-as-RAM"
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ hex "Length in bytes of cache-as-RAM"
+ default 0x80000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
config CPU_ADDR_BITS
int
default 36