blob: a0b8d5f5be1663ecf6234e9f8d120025ce7da320 [file] [log] [blame]
Angel Ponsc74dae92020-04-02 23:48:16 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Andrew Wub7bb70d2013-08-12 20:07:47 +08002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
Andrew Wub7bb70d2013-08-12 20:07:47 +08006#include <device/azalia_device.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02007#include <device/mmio.h>
Andrew Wub7bb70d2013-08-12 20:07:47 +08008#include <delay.h>
Patrick Rudolph9f5261e2021-02-16 09:18:07 +01009#include <timer.h>
Andrew Wub7bb70d2013-08-12 20:07:47 +080010
Angel Pons61dd8362020-12-05 18:02:32 +010011int azalia_set_bits(void *port, u32 mask, u32 val)
Andrew Wub7bb70d2013-08-12 20:07:47 +080012{
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010013 struct stopwatch sw;
Andrew Wub7bb70d2013-08-12 20:07:47 +080014 u32 reg32;
Andrew Wub7bb70d2013-08-12 20:07:47 +080015
16 /* Write (val & mask) to port */
17 val &= mask;
18 reg32 = read32(port);
19 reg32 &= ~mask;
20 reg32 |= val;
21 write32(port, reg32);
22
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +020023 /* Wait for readback of register to match what was just written to it */
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010024 stopwatch_init_msecs_expire(&sw, 50);
Andrew Wub7bb70d2013-08-12 20:07:47 +080025 do {
26 /* Wait 1ms based on BKDG wait time */
27 mdelay(1);
28 reg32 = read32(port);
29 reg32 &= mask;
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010030 } while ((reg32 != val) && !stopwatch_expired(&sw));
Andrew Wub7bb70d2013-08-12 20:07:47 +080031
32 /* Timeout occurred */
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010033 if (stopwatch_expired(&sw))
Andrew Wub7bb70d2013-08-12 20:07:47 +080034 return -1;
35 return 0;
36}
37
Angel Pons49190282020-12-05 18:52:38 +010038int azalia_enter_reset(u8 *base)
39{
40 /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
41 return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
42}
43
44int azalia_exit_reset(u8 *base)
45{
46 /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
47 return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
48}
49
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080050static int codec_detect(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +080051{
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010052 struct stopwatch sw;
Andrew Wub7bb70d2013-08-12 20:07:47 +080053 u32 reg32;
Andrew Wub7bb70d2013-08-12 20:07:47 +080054
Angel Pons7f839f62020-12-05 19:02:14 +010055 if (azalia_exit_reset(base) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080056 goto no_codec;
57
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +020058 /* clear STATESTS bits (BAR + 0xe)[2:0] */
Elyes HAOUASd8c47992020-08-03 15:31:39 +020059 reg32 = read32(base + HDA_STATESTS_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +080060 reg32 |= 7;
Elyes HAOUASd8c47992020-08-03 15:31:39 +020061 write32(base + HDA_STATESTS_REG, reg32);
Andrew Wub7bb70d2013-08-12 20:07:47 +080062
63 /* Wait for readback of register to
64 * match what was just written to it
65 */
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010066 stopwatch_init_msecs_expire(&sw, 50);
Andrew Wub7bb70d2013-08-12 20:07:47 +080067 do {
68 /* Wait 1ms based on BKDG wait time */
69 mdelay(1);
Elyes HAOUASd8c47992020-08-03 15:31:39 +020070 reg32 = read32(base + HDA_STATESTS_REG);
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010071 } while ((reg32 != 0) && !stopwatch_expired(&sw));
72
Martin Roth2ed0aa22016-01-05 20:58:58 -070073 /* Timeout occurred */
Patrick Rudolph9f5261e2021-02-16 09:18:07 +010074 if (stopwatch_expired(&sw))
Andrew Wub7bb70d2013-08-12 20:07:47 +080075 goto no_codec;
76
Angel Pons2e0053b2020-12-05 19:06:55 +010077 if (azalia_enter_reset(base) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080078 goto no_codec;
79
Angel Pons7f839f62020-12-05 19:02:14 +010080 if (azalia_exit_reset(base) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080081 goto no_codec;
82
83 /* Read in Codec location (BAR + 0xe)[2..0] */
Elyes HAOUASd8c47992020-08-03 15:31:39 +020084 reg32 = read32(base + HDA_STATESTS_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +080085 reg32 &= 0x0f;
86 if (!reg32)
87 goto no_codec;
88
89 return reg32;
90
91no_codec:
92 /* Codec Not found */
93 /* Put HDA back in reset (BAR + 0x8) [0] */
Angel Pons61dd8362020-12-05 18:02:32 +010094 azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
Andrew Wub7bb70d2013-08-12 20:07:47 +080095 printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
96 return 0;
97}
98
Angel Ponsd3f70282020-12-05 18:28:33 +010099/*
100 * Find a specific entry within a verb table
101 *
102 * @param verb_table: verb table data
103 * @param verb_table_bytes: verb table size in bytes
104 * @param viddid: vendor/device to search for
105 * @param verb: pointer to entry within table
106 *
107 * Returns size of the entry within the verb table,
108 * Returns 0 if the entry is not found
109 *
110 * The HDA verb table is composed of dwords. A set of 4 dwords is
111 * grouped together to form a "jack" descriptor.
112 * Bits 31:28 - Codec Address
113 * Bits 27:20 - NID
114 * Bits 19:8 - Verb ID
115 * Bits 7:0 - Payload
116 *
117 * coreboot groups different codec verb tables into a single table
118 * and prefixes each with a specific header consisting of 3
119 * dword entries:
120 * 1 - Codec Vendor/Device ID
121 * 2 - Subsystem ID
122 * 3 - Number of jacks (groups of 4 dwords) for this codec
123 */
Angel Ponsd425ddd2020-12-05 18:22:58 +0100124u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800125{
Andrew Wub7bb70d2013-08-12 20:07:47 +0800126 int idx = 0;
127
Angel Ponsd425ddd2020-12-05 18:22:58 +0100128 while (idx < (verb_table_bytes / sizeof(u32))) {
Angel Ponsf23c6a82020-12-05 18:32:05 +0100129 /* Header contains the number of jacks, aka groups of 4 dwords */
130 u32 verb_size = 4 * verb_table[idx + 2];
Angel Ponsd425ddd2020-12-05 18:22:58 +0100131 if (verb_table[idx] != viddid) {
Andrew Wub7bb70d2013-08-12 20:07:47 +0800132 idx += verb_size + 3; // skip verb + header
133 continue;
134 }
Angel Ponsd425ddd2020-12-05 18:22:58 +0100135 *verb = &verb_table[idx + 3];
Andrew Wub7bb70d2013-08-12 20:07:47 +0800136 return verb_size;
137 }
138
139 /* Not all codecs need to load another verb */
140 return 0;
141}
142
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200143/*
144 * Wait 50usec for the codec to indicate it is ready.
145 * No response would imply that the codec is non-operative.
Andrew Wub7bb70d2013-08-12 20:07:47 +0800146 */
147
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800148static int wait_for_ready(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800149{
Patrick Rudolph9f5261e2021-02-16 09:18:07 +0100150 struct stopwatch sw;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200151 /* Use a 50 usec timeout - the Linux kernel uses the same duration */
Patrick Rudolph9f5261e2021-02-16 09:18:07 +0100152 stopwatch_init_usecs_expire(&sw, 50);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800153
Patrick Rudolph9f5261e2021-02-16 09:18:07 +0100154 while (!stopwatch_expired(&sw)) {
Andrew Wub7bb70d2013-08-12 20:07:47 +0800155 u32 reg32 = read32(base + HDA_ICII_REG);
156 if (!(reg32 & HDA_ICII_BUSY))
157 return 0;
158 udelay(1);
159 }
160
161 return -1;
162}
163
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200164/*
Angel Ponsfa1befc2021-03-18 14:12:32 +0100165 * Wait for the codec to indicate that it accepted the previous command.
166 * No response would imply that the codec is non-operative.
Andrew Wub7bb70d2013-08-12 20:07:47 +0800167 */
168
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800169static int wait_for_valid(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800170{
Patrick Rudolph9f5261e2021-02-16 09:18:07 +0100171 struct stopwatch sw;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200172 u32 reg32;
Andrew Wub7bb70d2013-08-12 20:07:47 +0800173
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200174 /* Send the verb to the codec */
175 reg32 = read32(base + HDA_ICII_REG);
176 reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
177 write32(base + HDA_ICII_REG, reg32);
178
Angel Ponsfa1befc2021-03-18 14:12:32 +0100179 /*
180 * The timeout is never reached when the codec is functioning properly.
181 * Using a small timeout value can result in spurious errors with some
182 * codecs, e.g. a codec that is slow to respond but operates correctly.
183 * When a codec is non-operative, the timeout is only reached once per
184 * verb table, thus the impact on booting time is relatively small. So,
185 * use a reasonably long enough timeout to cover all possible cases.
186 */
187 stopwatch_init_msecs_expire(&sw, 1);
Patrick Rudolph9f5261e2021-02-16 09:18:07 +0100188 while (!stopwatch_expired(&sw)) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200189 reg32 = read32(base + HDA_ICII_REG);
190 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800191 return 0;
192 udelay(1);
193 }
194
195 return -1;
196}
197
Angel Pons44c431e2021-02-08 12:37:56 +0100198static int azalia_write_verb(u8 *base, u32 verb)
199{
200 if (wait_for_ready(base) < 0)
201 return -1;
202
203 write32(base + HDA_IC_REG, verb);
204
205 return wait_for_valid(base);
206}
207
208int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size)
209{
210 if (!verbs)
211 return 0;
212
213 for (u32 i = 0; i < verb_size; i++) {
214 if (azalia_write_verb(base, verbs[i]) < 0)
215 return -1;
216 }
217 return 0;
218}
219
Angel Ponsd6d71ce2021-02-08 12:47:29 +0100220__weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
221{
222}
223
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800224static void codec_init(struct device *dev, u8 *base, int addr)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800225{
226 u32 reg32;
227 const u32 *verb;
228 u32 verb_size;
Andrew Wub7bb70d2013-08-12 20:07:47 +0800229
230 printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr);
231
232 /* 1 */
Angel Pons554713e2020-10-24 23:23:07 +0200233 if (wait_for_ready(base) < 0) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200234 printk(BIOS_DEBUG, " codec not ready.\n");
Andrew Wub7bb70d2013-08-12 20:07:47 +0800235 return;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200236 }
Andrew Wub7bb70d2013-08-12 20:07:47 +0800237
238 reg32 = (addr << 28) | 0x000f0000;
Elyes HAOUASd8c47992020-08-03 15:31:39 +0200239 write32(base + HDA_IC_REG, reg32);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800240
Angel Pons554713e2020-10-24 23:23:07 +0200241 if (wait_for_valid(base) < 0) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200242 printk(BIOS_DEBUG, " codec not valid.\n");
Andrew Wub7bb70d2013-08-12 20:07:47 +0800243 return;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200244 }
Andrew Wub7bb70d2013-08-12 20:07:47 +0800245
246 /* 2 */
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200247 reg32 = read32(base + HDA_IR_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800248 printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
Angel Ponsd425ddd2020-12-05 18:22:58 +0100249 verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800250
251 if (!verb_size) {
252 printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
253 return;
254 }
Angel Pons2e774432021-02-08 12:40:06 +0100255 printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800256
257 /* 3 */
Angel Pons44c431e2021-02-08 12:37:56 +0100258 azalia_program_verb_table(base, verb, verb_size);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800259 printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
Angel Ponsd6d71ce2021-02-08 12:47:29 +0100260
261 mainboard_azalia_program_runtime_verbs(base, reg32);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800262}
263
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800264static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800265{
266 int i;
267
268 for (i = 2; i >= 0; i--) {
269 if (codec_mask & (1 << i))
270 codec_init(dev, base, i);
271 }
272}
273
274void azalia_audio_init(struct device *dev)
275{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800276 u8 *base;
Andrew Wub7bb70d2013-08-12 20:07:47 +0800277 struct resource *res;
278 u32 codec_mask;
279
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200280 res = find_resource(dev, PCI_BASE_ADDRESS_0);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800281 if (!res)
282 return;
283
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200284 // NOTE this will break as soon as the azalia_audio get's a bar above 4G.
285 // Is there anything we can do about it?
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800286 base = res2mmio(res, 0, 0);
287 printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800288 codec_mask = codec_detect(base);
289
290 if (codec_mask) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200291 printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800292 codecs_init(dev, base, codec_mask);
293 }
294}
295
Andrew Wub7bb70d2013-08-12 20:07:47 +0800296struct device_operations default_azalia_audio_ops = {
297 .read_resources = pci_dev_read_resources,
298 .set_resources = pci_dev_set_resources,
299 .enable_resources = pci_dev_enable_resources,
300 .init = azalia_audio_init,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200301 .ops_pci = &pci_dev_ops_pci,
Andrew Wub7bb70d2013-08-12 20:07:47 +0800302};