blob: 9306e2ac3709d34bd6dd91195dfae448bb4dd497 [file] [log] [blame]
Angel Ponsc74dae92020-04-02 23:48:16 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Andrew Wub7bb70d2013-08-12 20:07:47 +08002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
Andrew Wub7bb70d2013-08-12 20:07:47 +08006#include <device/azalia_device.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02007#include <device/mmio.h>
Andrew Wub7bb70d2013-08-12 20:07:47 +08008#include <delay.h>
9
Angel Pons61dd8362020-12-05 18:02:32 +010010int azalia_set_bits(void *port, u32 mask, u32 val)
Andrew Wub7bb70d2013-08-12 20:07:47 +080011{
12 u32 reg32;
13 int count;
14
15 /* Write (val & mask) to port */
16 val &= mask;
17 reg32 = read32(port);
18 reg32 &= ~mask;
19 reg32 |= val;
20 write32(port, reg32);
21
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +020022 /* Wait for readback of register to match what was just written to it */
Andrew Wub7bb70d2013-08-12 20:07:47 +080023 count = 50;
24 do {
25 /* Wait 1ms based on BKDG wait time */
26 mdelay(1);
27 reg32 = read32(port);
28 reg32 &= mask;
29 } while ((reg32 != val) && --count);
30
31 /* Timeout occurred */
32 if (!count)
33 return -1;
34 return 0;
35}
36
Angel Pons49190282020-12-05 18:52:38 +010037int azalia_enter_reset(u8 *base)
38{
39 /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
40 return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
41}
42
43int azalia_exit_reset(u8 *base)
44{
45 /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
46 return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
47}
48
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080049static int codec_detect(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +080050{
51 u32 reg32;
52 int count;
53
54 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
Angel Pons61dd8362020-12-05 18:02:32 +010055 if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080056 goto no_codec;
57
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +020058 /* clear STATESTS bits (BAR + 0xe)[2:0] */
Elyes HAOUASd8c47992020-08-03 15:31:39 +020059 reg32 = read32(base + HDA_STATESTS_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +080060 reg32 |= 7;
Elyes HAOUASd8c47992020-08-03 15:31:39 +020061 write32(base + HDA_STATESTS_REG, reg32);
Andrew Wub7bb70d2013-08-12 20:07:47 +080062
63 /* Wait for readback of register to
64 * match what was just written to it
65 */
66 count = 50;
67 do {
68 /* Wait 1ms based on BKDG wait time */
69 mdelay(1);
Elyes HAOUASd8c47992020-08-03 15:31:39 +020070 reg32 = read32(base + HDA_STATESTS_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +080071 } while ((reg32 != 0) && --count);
Martin Roth2ed0aa22016-01-05 20:58:58 -070072 /* Timeout occurred */
Andrew Wub7bb70d2013-08-12 20:07:47 +080073 if (!count)
74 goto no_codec;
75
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +020076 /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
Angel Pons61dd8362020-12-05 18:02:32 +010077 if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080078 goto no_codec;
79
80 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
Angel Pons61dd8362020-12-05 18:02:32 +010081 if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +080082 goto no_codec;
83
84 /* Read in Codec location (BAR + 0xe)[2..0] */
Elyes HAOUASd8c47992020-08-03 15:31:39 +020085 reg32 = read32(base + HDA_STATESTS_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +080086 reg32 &= 0x0f;
87 if (!reg32)
88 goto no_codec;
89
90 return reg32;
91
92no_codec:
93 /* Codec Not found */
94 /* Put HDA back in reset (BAR + 0x8) [0] */
Angel Pons61dd8362020-12-05 18:02:32 +010095 azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
Andrew Wub7bb70d2013-08-12 20:07:47 +080096 printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
97 return 0;
98}
99
Angel Ponsd3f70282020-12-05 18:28:33 +0100100/*
101 * Find a specific entry within a verb table
102 *
103 * @param verb_table: verb table data
104 * @param verb_table_bytes: verb table size in bytes
105 * @param viddid: vendor/device to search for
106 * @param verb: pointer to entry within table
107 *
108 * Returns size of the entry within the verb table,
109 * Returns 0 if the entry is not found
110 *
111 * The HDA verb table is composed of dwords. A set of 4 dwords is
112 * grouped together to form a "jack" descriptor.
113 * Bits 31:28 - Codec Address
114 * Bits 27:20 - NID
115 * Bits 19:8 - Verb ID
116 * Bits 7:0 - Payload
117 *
118 * coreboot groups different codec verb tables into a single table
119 * and prefixes each with a specific header consisting of 3
120 * dword entries:
121 * 1 - Codec Vendor/Device ID
122 * 2 - Subsystem ID
123 * 3 - Number of jacks (groups of 4 dwords) for this codec
124 */
Angel Ponsd425ddd2020-12-05 18:22:58 +0100125u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800126{
Andrew Wub7bb70d2013-08-12 20:07:47 +0800127 int idx = 0;
128
Angel Ponsd425ddd2020-12-05 18:22:58 +0100129 while (idx < (verb_table_bytes / sizeof(u32))) {
Angel Ponsf23c6a82020-12-05 18:32:05 +0100130 /* Header contains the number of jacks, aka groups of 4 dwords */
131 u32 verb_size = 4 * verb_table[idx + 2];
Angel Ponsd425ddd2020-12-05 18:22:58 +0100132 if (verb_table[idx] != viddid) {
Andrew Wub7bb70d2013-08-12 20:07:47 +0800133 idx += verb_size + 3; // skip verb + header
134 continue;
135 }
Angel Ponsd425ddd2020-12-05 18:22:58 +0100136 *verb = &verb_table[idx + 3];
Andrew Wub7bb70d2013-08-12 20:07:47 +0800137 return verb_size;
138 }
139
140 /* Not all codecs need to load another verb */
141 return 0;
142}
143
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200144/*
145 * Wait 50usec for the codec to indicate it is ready.
146 * No response would imply that the codec is non-operative.
Andrew Wub7bb70d2013-08-12 20:07:47 +0800147 */
148
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800149static int wait_for_ready(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800150{
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200151 /* Use a 50 usec timeout - the Linux kernel uses the same duration */
Andrew Wub7bb70d2013-08-12 20:07:47 +0800152 int timeout = 50;
153
154 while (timeout--) {
155 u32 reg32 = read32(base + HDA_ICII_REG);
156 if (!(reg32 & HDA_ICII_BUSY))
157 return 0;
158 udelay(1);
159 }
160
161 return -1;
162}
163
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200164/*
165 * Wait 50usec for the codec to indicate that it accepted the previous command.
166 * No response would imply that the code is non-operative.
Andrew Wub7bb70d2013-08-12 20:07:47 +0800167 */
168
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800169static int wait_for_valid(u8 *base)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800170{
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200171 u32 reg32;
172 /* Use a 50 usec timeout - the Linux kernel uses the same duration */
Andrew Wub7bb70d2013-08-12 20:07:47 +0800173 int timeout = 25;
174
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200175 /* Send the verb to the codec */
176 reg32 = read32(base + HDA_ICII_REG);
177 reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
178 write32(base + HDA_ICII_REG, reg32);
179
Andrew Wub7bb70d2013-08-12 20:07:47 +0800180 while (timeout--) {
181 udelay(1);
182 }
183 timeout = 50;
184 while (timeout--) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200185 reg32 = read32(base + HDA_ICII_REG);
186 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800187 return 0;
188 udelay(1);
189 }
190
191 return -1;
192}
193
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800194static void codec_init(struct device *dev, u8 *base, int addr)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800195{
196 u32 reg32;
197 const u32 *verb;
198 u32 verb_size;
199 int i;
200
201 printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr);
202
203 /* 1 */
Angel Pons554713e2020-10-24 23:23:07 +0200204 if (wait_for_ready(base) < 0) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200205 printk(BIOS_DEBUG, " codec not ready.\n");
Andrew Wub7bb70d2013-08-12 20:07:47 +0800206 return;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200207 }
Andrew Wub7bb70d2013-08-12 20:07:47 +0800208
209 reg32 = (addr << 28) | 0x000f0000;
Elyes HAOUASd8c47992020-08-03 15:31:39 +0200210 write32(base + HDA_IC_REG, reg32);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800211
Angel Pons554713e2020-10-24 23:23:07 +0200212 if (wait_for_valid(base) < 0) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200213 printk(BIOS_DEBUG, " codec not valid.\n");
Andrew Wub7bb70d2013-08-12 20:07:47 +0800214 return;
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200215 }
Andrew Wub7bb70d2013-08-12 20:07:47 +0800216
217 /* 2 */
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200218 reg32 = read32(base + HDA_IR_REG);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800219 printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
Angel Ponsd425ddd2020-12-05 18:22:58 +0100220 verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800221
222 if (!verb_size) {
223 printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
224 return;
225 }
226 printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size);
227
228 /* 3 */
229 for (i = 0; i < verb_size; i++) {
Angel Pons554713e2020-10-24 23:23:07 +0200230 if (wait_for_ready(base) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800231 return;
232
Elyes HAOUASd8c47992020-08-03 15:31:39 +0200233 write32(base + HDA_IC_REG, verb[i]);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800234
Angel Pons554713e2020-10-24 23:23:07 +0200235 if (wait_for_valid(base) < 0)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800236 return;
237 }
238 printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
239}
240
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800241static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
Andrew Wub7bb70d2013-08-12 20:07:47 +0800242{
243 int i;
244
245 for (i = 2; i >= 0; i--) {
246 if (codec_mask & (1 << i))
247 codec_init(dev, base, i);
248 }
249}
250
251void azalia_audio_init(struct device *dev)
252{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800253 u8 *base;
Andrew Wub7bb70d2013-08-12 20:07:47 +0800254 struct resource *res;
255 u32 codec_mask;
256
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200257 res = find_resource(dev, PCI_BASE_ADDRESS_0);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800258 if (!res)
259 return;
260
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200261 // NOTE this will break as soon as the azalia_audio get's a bar above 4G.
262 // Is there anything we can do about it?
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800263 base = res2mmio(res, 0, 0);
264 printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800265 codec_mask = codec_detect(base);
266
267 if (codec_mask) {
Elyes HAOUAS6ea24ff2020-08-11 09:21:24 +0200268 printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
Andrew Wub7bb70d2013-08-12 20:07:47 +0800269 codecs_init(dev, base, codec_mask);
270 }
271}
272
Andrew Wub7bb70d2013-08-12 20:07:47 +0800273struct device_operations default_azalia_audio_ops = {
274 .read_resources = pci_dev_read_resources,
275 .set_resources = pci_dev_set_resources,
276 .enable_resources = pci_dev_enable_resources,
277 .init = azalia_audio_init,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200278 .ops_pci = &pci_dev_ops_pci,
Andrew Wub7bb70d2013-08-12 20:07:47 +0800279};