Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE_BASE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 2 | bool |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 3 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 4 | config SOC_INTEL_COFFEELAKE |
| 5 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 6 | select SOC_INTEL_CANNONLAKE_BASE |
Nico Huber | bf15b2f | 2019-12-13 13:44:04 +0100 | [diff] [blame] | 7 | select FSP_USES_CB_STACK |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 8 | select HAVE_INTEL_FSP_REPO |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 9 | select SOC_INTEL_CONFIGURE_DDI_A_4_LANES |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 10 | help |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 11 | Intel Coffeelake support |
| 12 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 13 | config SOC_INTEL_WHISKEYLAKE |
| 14 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 15 | select SOC_INTEL_CANNONLAKE_BASE |
Bora Guvendik | 349b6a1 | 2019-06-24 14:33:31 -0700 | [diff] [blame] | 16 | select FSP_USES_CB_STACK |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 17 | select HAVE_INTEL_FSP_REPO |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 18 | select SOC_INTEL_CONFIGURE_DDI_A_4_LANES |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 19 | help |
| 20 | Intel Whiskeylake support |
| 21 | |
Subrata Banik | fa011db | 2019-02-02 13:25:14 +0530 | [diff] [blame] | 22 | config SOC_INTEL_COMETLAKE |
| 23 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 24 | select SOC_INTEL_CANNONLAKE_BASE |
Aamir Bohra | f2ad8b3 | 2019-07-08 12:22:28 +0530 | [diff] [blame] | 25 | select FSP_USES_CB_STACK |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 26 | select HAVE_INTEL_FSP_REPO |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 27 | select SOC_INTEL_CONFIGURE_DDI_A_4_LANES |
Subrata Banik | fa011db | 2019-02-02 13:25:14 +0530 | [diff] [blame] | 28 | help |
| 29 | Intel Cometlake support |
| 30 | |
Felix Singer | e1af5b8 | 2020-08-31 19:51:52 +0000 | [diff] [blame] | 31 | config SOC_INTEL_COMETLAKE_1 |
| 32 | bool |
| 33 | select SOC_INTEL_COMETLAKE |
| 34 | |
Felix Singer | 923b175 | 2020-08-31 19:56:53 +0000 | [diff] [blame] | 35 | config SOC_INTEL_COMETLAKE_2 |
| 36 | bool |
| 37 | select SOC_INTEL_COMETLAKE |
| 38 | |
| 39 | config SOC_INTEL_COMETLAKE_S |
| 40 | bool |
| 41 | select SOC_INTEL_COMETLAKE |
| 42 | |
| 43 | config SOC_INTEL_COMETLAKE_V |
| 44 | bool |
| 45 | select SOC_INTEL_COMETLAKE |
| 46 | |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 47 | config SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 48 | bool |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 49 | help |
| 50 | Choose this option if you have a PCH-H chipset. |
| 51 | |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 52 | if SOC_INTEL_CANNONLAKE_BASE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 53 | |
| 54 | config CPU_SPECIFIC_OPTIONS |
| 55 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 56 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 57 | select ACPI_NHLT |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 58 | select ARCH_ALL_STAGES_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 59 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 60 | select CACHE_MRC_SETTINGS |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 61 | select CPU_INTEL_COMMON |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 62 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 63 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 64 | select DISPLAY_FSP_VERSION_INFO |
Karthikeyan Ramasubramanian | 203af60 | 2020-06-17 00:12:31 -0600 | [diff] [blame] | 65 | select FSP_COMPRESS_FSP_S_LZMA |
Furquan Shaikh | cef9879 | 2019-04-10 16:31:55 -0700 | [diff] [blame] | 66 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 67 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 68 | select FSP_T_XIP if FSP_CAR |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 69 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 70 | select HAVE_FSP_GOP |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 71 | select HAVE_FSP_LOGO_SUPPORT |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 72 | select HAVE_SMI_HANDLER |
Aamir Bohra | e462585 | 2018-05-29 10:52:33 +0530 | [diff] [blame] | 73 | select IDT_IN_EVERY_STAGE |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 74 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 75 | select INTEL_GMA_ACPI |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 76 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 77 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 78 | select MRC_SETTINGS_PROTECT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 79 | select PARALLEL_MP |
| 80 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 81 | select PLATFORM_USES_FSP2_0 |
Michael Niewöhner | a1843d8 | 2020-10-02 18:28:22 +0200 | [diff] [blame] | 82 | select PM_ACPI_TIMER_OPTIONAL |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 83 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 84 | select REG_SCRIPT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 85 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 87 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | c66e1c2 | 2020-11-12 23:50:37 +0100 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 320a3ab | 2021-01-01 21:14:16 +0100 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 93 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 94 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 95 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 96 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Tim Wawrzynczak | 939440c | 2019-04-26 15:03:33 -0600 | [diff] [blame] | 97 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 98 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
praveen hodagatta pranesh | dc4fceb | 2018-10-16 18:06:18 +0800 | [diff] [blame] | 99 | select SOC_INTEL_COMMON_BLOCK_HDA |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 100 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 101 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 102 | select SOC_INTEL_COMMON_BLOCK_SCS |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 103 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 104 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 2fff391 | 2020-01-16 10:13:28 +0530 | [diff] [blame] | 105 | select SOC_INTEL_COMMON_BLOCK_THERMAL |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 106 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 107 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 108 | select SOC_INTEL_COMMON_FSP_RESET |
Felix Singer | 30fd5bf | 2020-12-07 10:37:10 +0100 | [diff] [blame] | 109 | select SOC_INTEL_COMMON_NHLT |
| 110 | select SOC_INTEL_COMMON_PCH_BASE |
| 111 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 112 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 113 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 114 | select TSC_MONOTONIC_TIMER |
| 115 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 116 | select UDK_2017_BINDING |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 117 | |
Edward O'Callaghan | b4a68a5 | 2019-12-15 13:30:38 +1100 | [diff] [blame] | 118 | config MAX_CPUS |
| 119 | int |
| 120 | default 12 |
| 121 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 122 | config DCACHE_RAM_BASE |
| 123 | default 0xfef00000 |
| 124 | |
| 125 | config DCACHE_RAM_SIZE |
| 126 | default 0x40000 |
| 127 | help |
| 128 | The size of the cache-as-ram region required during bootblock |
| 129 | and/or romstage. |
| 130 | |
| 131 | config DCACHE_BSP_STACK_SIZE |
| 132 | hex |
V Sowmya | 1dcc170 | 2019-10-14 14:42:34 +0530 | [diff] [blame] | 133 | default 0x20400 if FSP_USES_CB_STACK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 134 | default 0x4000 |
| 135 | help |
| 136 | The amount of anticipated stack usage in CAR by bootblock and |
V Sowmya | 1dcc170 | 2019-10-14 14:42:34 +0530 | [diff] [blame] | 137 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 138 | sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 139 | |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 140 | config FSP_TEMP_RAM_SIZE |
| 141 | hex |
| 142 | depends on FSP_USES_CB_STACK |
| 143 | default 0x10000 |
| 144 | help |
| 145 | The amount of anticipated heap usage in CAR by FSP. |
| 146 | Refer to Platform FSP integration guide document to know |
| 147 | the exact FSP requirement for Heap setup. |
| 148 | |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 149 | config IFD_CHIPSET |
| 150 | string |
| 151 | default "cnl" |
| 152 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 153 | config IED_REGION_SIZE |
| 154 | hex |
| 155 | default 0x400000 |
| 156 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 157 | config HEAP_SIZE |
| 158 | hex |
| 159 | default 0x8000 |
| 160 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 161 | config NHLT_DMIC_1CH_16B |
| 162 | bool |
| 163 | depends on ACPI_NHLT |
| 164 | default n |
| 165 | help |
| 166 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 167 | |
| 168 | config NHLT_DMIC_2CH_16B |
| 169 | bool |
| 170 | depends on ACPI_NHLT |
| 171 | default n |
| 172 | help |
| 173 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 174 | |
| 175 | config NHLT_DMIC_4CH_16B |
| 176 | bool |
| 177 | depends on ACPI_NHLT |
| 178 | default n |
| 179 | help |
| 180 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 181 | |
| 182 | config NHLT_MAX98357 |
| 183 | bool |
| 184 | depends on ACPI_NHLT |
| 185 | default n |
| 186 | help |
| 187 | Include DSP firmware settings for headset codec. |
| 188 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 189 | config NHLT_MAX98373 |
| 190 | bool |
| 191 | depends on ACPI_NHLT |
| 192 | default n |
| 193 | help |
| 194 | Include DSP firmware settings for headset codec. |
| 195 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 196 | config NHLT_DA7219 |
| 197 | bool |
| 198 | depends on ACPI_NHLT |
| 199 | default n |
| 200 | help |
| 201 | Include DSP firmware settings for headset codec. |
| 202 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 203 | config MAX_ROOT_PORTS |
| 204 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 205 | default 24 if SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 206 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 207 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 208 | config MAX_PCIE_CLOCK_SRC |
Lijian Zhao | d5d89c8 | 2019-05-07 14:05:33 -0700 | [diff] [blame] | 209 | int |
| 210 | default 16 if SOC_INTEL_CANNONLAKE_PCH_H |
| 211 | default 6 |
| 212 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 213 | config SMM_TSEG_SIZE |
| 214 | hex |
| 215 | default 0x800000 |
| 216 | |
Subrata Banik | e66600e | 2018-05-10 17:23:56 +0530 | [diff] [blame] | 217 | config SMM_RESERVED_SIZE |
| 218 | hex |
| 219 | default 0x200000 |
| 220 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 221 | config PCR_BASE_ADDRESS |
| 222 | hex |
| 223 | default 0xfd000000 |
| 224 | help |
| 225 | This option allows you to select MMIO Base Address of sideband bus. |
| 226 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 227 | config CPU_BCLK_MHZ |
| 228 | int |
| 229 | default 100 |
| 230 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 231 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 232 | int |
| 233 | default 120 |
| 234 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 235 | config CPU_XTAL_HZ |
| 236 | default 24000000 |
| 237 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 238 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 239 | int |
Duncan Laurie | 695f2fe | 2018-12-05 12:51:23 -0800 | [diff] [blame] | 240 | default 216 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 241 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 242 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 243 | int |
| 244 | default 3 |
| 245 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 246 | config SOC_INTEL_I2C_DEV_MAX |
| 247 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 248 | default 4 if SOC_INTEL_CANNONLAKE_PCH_H |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 249 | default 6 |
| 250 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 251 | config CONSOLE_UART_BASE_ADDRESS |
| 252 | hex |
| 253 | default 0xfe032000 |
| 254 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 255 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 256 | # Clock divider parameters for 115200 baud rate |
| 257 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 258 | hex |
| 259 | default 0x30 |
| 260 | |
| 261 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 262 | hex |
| 263 | default 0xc35 |
| 264 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 265 | config VBOOT |
| 266 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 267 | select VBOOT_MUST_REQUEST_DISPLAY |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 268 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 269 | select VBOOT_VBNV_CMOS |
| 270 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 271 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 272 | config CBFS_SIZE |
| 273 | hex |
| 274 | default 0x200000 |
| 275 | |
Rizwan Qureshi | 8aadab7 | 2019-02-17 11:31:21 +0530 | [diff] [blame] | 276 | config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE |
| 277 | bool |
| 278 | default n |
| 279 | help |
| 280 | Select this if the board has a SD_PWR_ENABLE pin connected to a |
| 281 | active high sensing load switch to turn on power to the card reader. |
| 282 | This will enable a workaround in ASL _PS3 and _PS0 methods to force |
| 283 | SD_PWR_ENABLE to stay low in D3. |
| 284 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 285 | choice |
| 286 | prompt "Cache-as-ram implementation" |
Angel Pons | 7ed704d | 2019-07-12 15:46:43 +0200 | [diff] [blame] | 287 | default USE_CANNONLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 288 | help |
| 289 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 290 | |
| 291 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 292 | bool "Enhanced Non-evict mode" |
| 293 | select SOC_INTEL_COMMON_BLOCK_CAR |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 294 | select INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 295 | help |
| 296 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 297 | sizes are derived from the requirement to not write out any modified |
| 298 | cache line. With NEM, if there is no physical memory behind the |
| 299 | cached area, the modified data will be lost and NEM results will be |
| 300 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 301 | kept in cache while clean data is replaced. |
| 302 | |
| 303 | config USE_CANNONLAKE_FSP_CAR |
| 304 | bool "Use FSP CAR" |
| 305 | select FSP_CAR |
| 306 | help |
| 307 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 308 | |
| 309 | endchoice |
| 310 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 311 | config FSP_HEADER_PATH |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 312 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
Felix Singer | e1af5b8 | 2020-08-31 19:51:52 +0000 | [diff] [blame] | 313 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1 |
Felix Singer | 923b175 | 2020-08-31 19:56:53 +0000 | [diff] [blame] | 314 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2 |
| 315 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S |
| 316 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 317 | |
| 318 | config FSP_FD_PATH |
Johanna Schander | 0b82b3d | 2019-12-06 18:32:58 +0100 | [diff] [blame] | 319 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
Felix Singer | dd9f635 | 2020-08-31 20:00:55 +0000 | [diff] [blame] | 320 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1 |
Felix Singer | 923b175 | 2020-08-31 19:56:53 +0000 | [diff] [blame] | 321 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2 |
| 322 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S |
| 323 | default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 324 | |
Kane Chen | 3717256 | 2019-04-11 21:55:20 +0800 | [diff] [blame] | 325 | config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT |
| 326 | int "Debug Consent for CNL" |
| 327 | # USB DBC is more common for developers so make this default to 3 if |
| 328 | # SOC_INTEL_DEBUG_CONSENT=y |
| 329 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 330 | default 0 |
| 331 | help |
| 332 | This is to control debug interface on SOC. |
| 333 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 334 | PlatformDebugConsent in FspmUpd.h has the details. |
| 335 | |
Subrata Banik | 5ee4c12 | 2019-07-05 06:43:46 +0530 | [diff] [blame] | 336 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 337 | hex |
| 338 | default 0xe00 |
| 339 | |
Patrick Rudolph | 5fffb5e | 2019-07-25 11:55:30 +0200 | [diff] [blame] | 340 | config INTEL_TXT_BIOSACM_ALIGNMENT |
| 341 | hex |
| 342 | default 0x40000 # 256KB |
| 343 | |
Michael Niewöhner | fca152c | 2020-12-20 18:01:26 +0100 | [diff] [blame] | 344 | config INTEL_GMA_BCLV_OFFSET |
| 345 | default 0xc8258 |
| 346 | |
| 347 | config INTEL_GMA_BCLV_WIDTH |
| 348 | default 32 |
| 349 | |
| 350 | config INTEL_GMA_BCLM_OFFSET |
| 351 | default 0xc8254 |
| 352 | |
| 353 | config INTEL_GMA_BCLM_WIDTH |
| 354 | default 32 |
| 355 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 356 | endif |