blob: f792e70ec3550e13db2c2d93b41732f2f2c6ec92 [file] [log] [blame]
Arthur Heymansc8db6332019-06-17 13:32:13 +02001config SOC_INTEL_CANNONLAKE_BASE
Lijian Zhao81096042017-05-02 18:54:44 -07002 bool
Lijian Zhao81096042017-05-02 18:54:44 -07003
Arthur Heymans4821a0e2019-06-18 13:19:29 +02004config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
Lijian Zhao3638a522018-07-12 17:16:11 -07005 bool
Arthur Heymansc8db6332019-06-17 13:32:13 +02006 default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE
Lijian Zhao3638a522018-07-12 17:16:11 -07007 help
Subrata Banik6527b1a2019-01-29 11:04:25 +05308 Single Kconfig option to select common base Cannonlake support.
9 This Kconfig will help to select majority of CNL SoC features.
10 Major difference that exist today between
Arthur Heymans4821a0e2019-06-18 13:19:29 +020011 SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
Subrata Banik6527b1a2019-01-29 11:04:25 +053012 are in FSP Header Files. Hence this Kconfig might help to select
13 required SoC support FSP headers. Any future Intel SoC would
14 like to make use of CNL support might just select this Kconfig.
15
Arthur Heymansc8db6332019-06-17 13:32:13 +020016config SOC_INTEL_CANNONLAKE
17 bool
18 select SOC_INTEL_CANNONLAKE_BASE
Arthur Heymansa4492902019-06-17 10:50:47 +020019 select MICROCODE_BLOB_NOT_IN_BLOB_REPO
Arthur Heymansc8db6332019-06-17 13:32:13 +020020 help
21 Intel Cannonlake support
22
Subrata Banik6527b1a2019-01-29 11:04:25 +053023config SOC_INTEL_COFFEELAKE
24 bool
Arthur Heymansc8db6332019-06-17 13:32:13 +020025 select SOC_INTEL_CANNONLAKE_BASE
Nico Huberbf15b2f2019-12-13 13:44:04 +010026 select FSP_USES_CB_STACK
Johanna Schander8a6e0362019-12-08 15:54:09 +010027 select HAVE_INTEL_FSP_REPO
Nico Huberdd274e22020-04-26 20:37:32 +020028 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Subrata Banik6527b1a2019-01-29 11:04:25 +053029 help
Lijian Zhao3638a522018-07-12 17:16:11 -070030 Intel Coffeelake support
31
Subrata Banik6527b1a2019-01-29 11:04:25 +053032config SOC_INTEL_WHISKEYLAKE
33 bool
Arthur Heymansc8db6332019-06-17 13:32:13 +020034 select SOC_INTEL_CANNONLAKE_BASE
Bora Guvendik349b6a12019-06-24 14:33:31 -070035 select FSP_USES_CB_STACK
Johanna Schander8a6e0362019-12-08 15:54:09 +010036 select HAVE_INTEL_FSP_REPO
Nico Huberdd274e22020-04-26 20:37:32 +020037 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Subrata Banik6527b1a2019-01-29 11:04:25 +053038 help
39 Intel Whiskeylake support
40
Subrata Banikfa011db2019-02-02 13:25:14 +053041config SOC_INTEL_COMETLAKE
42 bool
Arthur Heymansc8db6332019-06-17 13:32:13 +020043 select SOC_INTEL_CANNONLAKE_BASE
Aamir Bohraf2ad8b32019-07-08 12:22:28 +053044 select FSP_USES_CB_STACK
Johanna Schander8a6e0362019-12-08 15:54:09 +010045 select HAVE_INTEL_FSP_REPO
Nico Huberdd274e22020-04-26 20:37:32 +020046 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Subrata Banikfa011db2019-02-02 13:25:14 +053047 help
48 Intel Cometlake support
49
Felix Singere1af5b82020-08-31 19:51:52 +000050config SOC_INTEL_COMETLAKE_1
51 bool
52 select SOC_INTEL_COMETLAKE
53
Felix Singer923b1752020-08-31 19:56:53 +000054config SOC_INTEL_COMETLAKE_2
55 bool
56 select SOC_INTEL_COMETLAKE
57
58config SOC_INTEL_COMETLAKE_S
59 bool
60 select SOC_INTEL_COMETLAKE
61
62config SOC_INTEL_COMETLAKE_V
63 bool
64 select SOC_INTEL_COMETLAKE
65
praveen hodagatta pranesh521e48c2018-09-27 00:00:13 +080066config SOC_INTEL_CANNONLAKE_PCH_H
Lijian Zhao3638a522018-07-12 17:16:11 -070067 bool
Lijian Zhao3638a522018-07-12 17:16:11 -070068 help
69 Choose this option if you have a PCH-H chipset.
70
Arthur Heymansc8db6332019-06-17 13:32:13 +020071if SOC_INTEL_CANNONLAKE_BASE
Lijian Zhao81096042017-05-02 18:54:44 -070072
73config CPU_SPECIFIC_OPTIONS
74 def_bool y
Lijian Zhaob3dfcb82017-08-16 22:18:52 -070075 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Lijian Zhao0e956f22017-10-22 18:30:39 -070076 select ACPI_NHLT
Angel Ponsa32df262020-09-25 10:20:11 +020077 select ARCH_ALL_STAGES_X86_32
Lijian Zhao32111172017-08-16 11:40:03 -070078 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
79 select BOOT_DEVICE_SUPPORTS_WRITES
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070080 select CACHE_MRC_SETTINGS
Ronak Kanabara432f382019-03-16 21:26:43 +053081 select CPU_INTEL_COMMON
Lijian Zhaoacfc1492017-07-06 15:27:27 -070082 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Karthikeyan Ramasubramanian203af602020-06-17 00:12:31 -060083 select FSP_COMPRESS_FSP_S_LZMA
Furquan Shaikhcef98792019-04-10 16:31:55 -070084 select FSP_M_XIP
Nick Vaccaro69b5cdb2017-08-29 19:25:23 -070085 select GENERIC_GPIO_LIB
Abhay kumarfcf88202017-09-20 15:17:42 -070086 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +010087 select HAVE_FSP_LOGO_SUPPORT
Stefan Tauneref8b9572018-09-06 00:34:28 +020088 select INTEL_DESCRIPTOR_MODE_CAPABLE
Lijian Zhaof0eb9992017-09-14 14:51:12 -070089 select HAVE_SMI_HANDLER
Aamir Bohrae4625852018-05-29 10:52:33 +053090 select IDT_IN_EVERY_STAGE
Abhay Kumarb0c4cbb2017-10-12 11:33:01 -070091 select INTEL_GMA_ACPI
Nico Huber29cc3312018-06-06 17:40:02 +020092 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lijian Zhaoa5158492017-08-29 14:37:17 -070093 select IOAPIC
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070094 select MRC_SETTINGS_PROTECT
Pratik Prajapati01eda282017-08-17 21:09:45 -070095 select PARALLEL_MP
96 select PARALLEL_MP_AP_WORK
Lijian Zhao81096042017-05-02 18:54:44 -070097 select PLATFORM_USES_FSP2_0
Lijian Zhaodcf99b02017-07-30 15:40:10 -070098 select REG_SCRIPT
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +020099 select PMC_GLOBAL_RESET_ENABLE_LOCK
Lijian Zhao81096042017-05-02 18:54:44 -0700100 select SOC_INTEL_COMMON
Lijian Zhao2b074d92017-08-17 14:25:24 -0700101 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Lijian Zhao81096042017-05-02 18:54:44 -0700102 select SOC_INTEL_COMMON_BLOCK
Lijian Zhao2b074d92017-08-17 14:25:24 -0700103 select SOC_INTEL_COMMON_BLOCK_ACPI
Subrata Banikc4986eb2018-05-09 14:55:09 +0530104 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Andrey Petrov3e2e0502017-06-05 13:22:24 -0700105 select SOC_INTEL_COMMON_BLOCK_CPU
Pratik Prajapati01eda282017-08-17 21:09:45 -0700106 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Tim Wawrzynczak939440c2019-04-26 15:03:33 -0600107 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Furquan Shaikha5bb7162017-12-20 11:09:04 -0800108 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
praveen hodagatta praneshdc4fceb2018-10-16 18:06:18 +0800109 select SOC_INTEL_COMMON_BLOCK_HDA
Lijian Zhaodcf99b02017-07-30 15:40:10 -0700110 select SOC_INTEL_COMMON_BLOCK_SA
Duncan Laurie1e066112020-04-08 11:35:52 -0700111 select SOC_INTEL_COMMON_BLOCK_SCS
Paul Fagerburg7803e482019-06-27 10:44:51 -0600112 select SOC_INTEL_COMMON_BLOCK_XHCI
113 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Brandon Breitensteinae154862017-08-01 11:32:06 -0700114 select SOC_INTEL_COMMON_BLOCK_SMM
115 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik2fff3912020-01-16 10:13:28 +0530116 select SOC_INTEL_COMMON_BLOCK_THERMAL
Subrata Banikf513ceb2018-05-17 15:57:43 +0530117 select SOC_INTEL_COMMON_PCH_BASE
Lijian Zhao0e956f22017-10-22 18:30:39 -0700118 select SOC_INTEL_COMMON_NHLT
Lijian Zhaodcf99b02017-07-30 15:40:10 -0700119 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikar309ccf72020-05-09 16:37:30 +0530120 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Lijian Zhaof0eb9992017-09-14 14:51:12 -0700121 select SSE2
Lijian Zhaoacfc1492017-07-06 15:27:27 -0700122 select SUPPORT_CPU_UCODE_IN_CBFS
Lijian Zhaodcf99b02017-07-30 15:40:10 -0700123 select TSC_MONOTONIC_TIMER
124 select UDELAY_TSC
Subrata Banik74558812018-01-25 11:41:04 +0530125 select UDK_2017_BINDING
Subrata Banika8733e32018-01-23 16:40:56 +0530126 select DISPLAY_FSP_VERSION_INFO
Praveen hodagatta praneshb66757f2018-10-23 02:43:05 +0800127 select FSP_T_XIP if FSP_CAR
Subrata Banika0368a02019-06-04 14:16:02 +0530128 select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
Lijian Zhao81096042017-05-02 18:54:44 -0700129
Edward O'Callaghanb4a68a52019-12-15 13:30:38 +1100130config MAX_CPUS
131 int
132 default 12
133
Lijian Zhao81096042017-05-02 18:54:44 -0700134config DCACHE_RAM_BASE
135 default 0xfef00000
136
137config DCACHE_RAM_SIZE
138 default 0x40000
139 help
140 The size of the cache-as-ram region required during bootblock
141 and/or romstage.
142
143config DCACHE_BSP_STACK_SIZE
144 hex
V Sowmya1dcc1702019-10-14 14:42:34 +0530145 default 0x20400 if FSP_USES_CB_STACK
Lijian Zhao81096042017-05-02 18:54:44 -0700146 default 0x4000
147 help
148 The amount of anticipated stack usage in CAR by bootblock and
V Sowmya1dcc1702019-10-14 14:42:34 +0530149 other stages. In the case of FSP_USES_CB_STACK default value will be
150 sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
Lijian Zhao81096042017-05-02 18:54:44 -0700151
Subrata Banik1d260e62019-09-09 13:55:42 +0530152config FSP_TEMP_RAM_SIZE
153 hex
154 depends on FSP_USES_CB_STACK
155 default 0x10000
156 help
157 The amount of anticipated heap usage in CAR by FSP.
158 Refer to Platform FSP integration guide document to know
159 the exact FSP requirement for Heap setup.
160
Furquan Shaikhc0257dd2018-05-02 23:29:04 -0700161config IFD_CHIPSET
162 string
163 default "cnl"
164
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700165config IED_REGION_SIZE
166 hex
167 default 0x400000
168
John Zhao7492bcb2018-02-01 15:56:28 -0800169config HEAP_SIZE
170 hex
171 default 0x8000
172
Lijian Zhao0e956f22017-10-22 18:30:39 -0700173config NHLT_DMIC_1CH_16B
174 bool
175 depends on ACPI_NHLT
176 default n
177 help
178 Include DSP firmware settings for 1 channel 16B DMIC array.
179
180config NHLT_DMIC_2CH_16B
181 bool
182 depends on ACPI_NHLT
183 default n
184 help
185 Include DSP firmware settings for 2 channel 16B DMIC array.
186
187config NHLT_DMIC_4CH_16B
188 bool
189 depends on ACPI_NHLT
190 default n
191 help
192 Include DSP firmware settings for 4 channel 16B DMIC array.
193
194config NHLT_MAX98357
195 bool
196 depends on ACPI_NHLT
197 default n
198 help
199 Include DSP firmware settings for headset codec.
200
N, Harshapriya4a1ee4b2017-11-28 14:29:26 -0800201config NHLT_MAX98373
202 bool
203 depends on ACPI_NHLT
204 default n
205 help
206 Include DSP firmware settings for headset codec.
207
Lijian Zhao0e956f22017-10-22 18:30:39 -0700208config NHLT_DA7219
209 bool
210 depends on ACPI_NHLT
211 default n
212 help
213 Include DSP firmware settings for headset codec.
214
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700215config MAX_ROOT_PORTS
216 int
praveen hodagatta pranesh521e48c2018-09-27 00:00:13 +0800217 default 24 if SOC_INTEL_CANNONLAKE_PCH_H
Lijian Zhaoc85890d2017-10-20 09:19:07 -0700218 default 16
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700219
Lijian Zhaod5d89c82019-05-07 14:05:33 -0700220config MAX_PCIE_CLOCKS
221 int
222 default 16 if SOC_INTEL_CANNONLAKE_PCH_H
223 default 6
224
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700225config SMM_TSEG_SIZE
226 hex
227 default 0x800000
228
Subrata Banike66600e2018-05-10 17:23:56 +0530229config SMM_RESERVED_SIZE
230 hex
231 default 0x200000
232
Lijian Zhao81096042017-05-02 18:54:44 -0700233config PCR_BASE_ADDRESS
234 hex
235 default 0xfd000000
236 help
237 This option allows you to select MMIO Base Address of sideband bus.
238
Andrey Petrov3e2e0502017-06-05 13:22:24 -0700239config CPU_BCLK_MHZ
240 int
241 default 100
242
Aaron Durbin551e4be2018-04-10 09:24:54 -0600243config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Lijian Zhaof3885612017-11-09 15:01:33 -0800244 int
245 default 120
246
Chris Chingb8dc63b2017-12-06 14:26:15 -0700247config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
248 int
Duncan Laurie695f2fe2018-12-05 12:51:23 -0800249 default 216
Chris Chingb8dc63b2017-12-06 14:26:15 -0700250
Lijian Zhao32111172017-08-16 11:40:03 -0700251config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
252 int
253 default 3
254
Subrata Banikc4986eb2018-05-09 14:55:09 +0530255config SOC_INTEL_I2C_DEV_MAX
256 int
praveen hodagatta pranesh521e48c2018-09-27 00:00:13 +0800257 default 4 if SOC_INTEL_CANNONLAKE_PCH_H
Subrata Banikc4986eb2018-05-09 14:55:09 +0530258 default 6
259
Nico Huber99954182019-05-29 23:33:06 +0200260config CONSOLE_UART_BASE_ADDRESS
261 hex
262 default 0xfe032000
263 depends on INTEL_LPSS_UART_FOR_CONSOLE
264
Lijian Zhao8465a812017-07-11 12:33:22 -0700265# Clock divider parameters for 115200 baud rate
266config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
267 hex
268 default 0x30
269
270config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
271 hex
272 default 0xc35
273
Lijian Zhao6d7063c2017-08-29 17:26:48 -0700274config CHROMEOS
275 select CHROMEOS_RAMOOPS_DYNAMIC
276
277config VBOOT
278 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800279 select VBOOT_MUST_REQUEST_DISPLAY
Lijian Zhao6d7063c2017-08-29 17:26:48 -0700280 select VBOOT_STARTS_IN_BOOTBLOCK
281 select VBOOT_VBNV_CMOS
282 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
283
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600284config C_ENV_BOOTBLOCK_SIZE
285 hex
Duncan Laurie11340e52018-12-01 16:58:52 -0800286 default 0xC000
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600287
Patrick Georgi6539e102018-09-13 11:48:43 -0400288config CBFS_SIZE
289 hex
290 default 0x200000
291
Rizwan Qureshi8aadab72019-02-17 11:31:21 +0530292config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
293 bool
294 default n
295 help
296 Select this if the board has a SD_PWR_ENABLE pin connected to a
297 active high sensing load switch to turn on power to the card reader.
298 This will enable a workaround in ASL _PS3 and _PS0 methods to force
299 SD_PWR_ENABLE to stay low in D3.
300
Subrata Banik9e3ba212018-01-08 15:28:26 +0530301choice
302 prompt "Cache-as-ram implementation"
Angel Pons7ed704d2019-07-12 15:46:43 +0200303 default USE_CANNONLAKE_CAR_NEM_ENHANCED
Subrata Banik9e3ba212018-01-08 15:28:26 +0530304 help
305 This option allows you to select how cache-as-ram (CAR) is set up.
306
307config USE_CANNONLAKE_CAR_NEM_ENHANCED
308 bool "Enhanced Non-evict mode"
309 select SOC_INTEL_COMMON_BLOCK_CAR
Aamir Bohrac1d227d2020-07-16 09:03:06 +0530310 select USE_CAR_NEM_ENHANCED_V1
Subrata Banik9e3ba212018-01-08 15:28:26 +0530311 help
312 A current limitation of NEM (Non-Evict mode) is that code and data
313 sizes are derived from the requirement to not write out any modified
314 cache line. With NEM, if there is no physical memory behind the
315 cached area, the modified data will be lost and NEM results will be
316 inconsistent. ENHANCED NEM guarantees that modified data is always
317 kept in cache while clean data is replaced.
318
319config USE_CANNONLAKE_FSP_CAR
320 bool "Use FSP CAR"
321 select FSP_CAR
322 help
323 Use FSP APIs to initialize and tear down the Cache-As-Ram.
324
325endchoice
326
Patrick Georgi6539e102018-09-13 11:48:43 -0400327config FSP_HEADER_PATH
Subrata Banik6527b1a2019-01-29 11:04:25 +0530328 default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
Felix Singere1af5b82020-08-31 19:51:52 +0000329 default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
Felix Singer923b1752020-08-31 19:56:53 +0000330 default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2
331 default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
332 default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
Arthur Heymansc8db6332019-06-17 13:32:13 +0200333 default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
Patrick Georgi6539e102018-09-13 11:48:43 -0400334
335config FSP_FD_PATH
Johanna Schander0b82b3d2019-12-06 18:32:58 +0100336 default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
Felix Singerdd9f6352020-08-31 20:00:55 +0000337 default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1
Felix Singer923b1752020-08-31 19:56:53 +0000338 default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2
339 default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S
340 default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V
Patrick Georgi6539e102018-09-13 11:48:43 -0400341
Kane Chen37172562019-04-11 21:55:20 +0800342config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
343 int "Debug Consent for CNL"
344 # USB DBC is more common for developers so make this default to 3 if
345 # SOC_INTEL_DEBUG_CONSENT=y
346 default 3 if SOC_INTEL_DEBUG_CONSENT
347 default 0
348 help
349 This is to control debug interface on SOC.
350 Setting non-zero value will allow to use DBC or DCI to debug SOC.
351 PlatformDebugConsent in FspmUpd.h has the details.
352
Subrata Banik5ee4c122019-07-05 06:43:46 +0530353config PRERAM_CBMEM_CONSOLE_SIZE
354 hex
355 default 0xe00
356
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200357config INTEL_TXT_BIOSACM_ALIGNMENT
358 hex
359 default 0x40000 # 256KB
360
Lijian Zhao81096042017-05-02 18:54:44 -0700361endif