blob: 898b4444d7c5956ae219f799c07ba41fddad45aa [file] [log] [blame]
Lijian Zhao81096042017-05-02 18:54:44 -07001config SOC_INTEL_CANNONLAKE
2 bool
3 help
4 Intel Cannonlake support
5
6if SOC_INTEL_CANNONLAKE
7
8config CPU_SPECIFIC_OPTIONS
9 def_bool y
Lijian Zhaob3dfcb82017-08-16 22:18:52 -070010 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Lijian Zhao0e956f22017-10-22 18:30:39 -070011 select ACPI_NHLT
Lijian Zhao81096042017-05-02 18:54:44 -070012 select ARCH_BOOTBLOCK_X86_32
Lijian Zhao81096042017-05-02 18:54:44 -070013 select ARCH_RAMSTAGE_X86_32
14 select ARCH_ROMSTAGE_X86_32
Lijian Zhaodcf99b02017-07-30 15:40:10 -070015 select ARCH_VERSTAGE_X86_32
Lijian Zhao32111172017-08-16 11:40:03 -070016 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
17 select BOOT_DEVICE_SUPPORTS_WRITES
Lijian Zhao81096042017-05-02 18:54:44 -070018 select C_ENVIRONMENT_BOOTBLOCK
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070019 select CACHE_MRC_SETTINGS
Lijian Zhao2b074d92017-08-17 14:25:24 -070020 select COMMON_FADT
Lijian Zhaoacfc1492017-07-06 15:27:27 -070021 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Nick Vaccaro69b5cdb2017-08-29 19:25:23 -070022 select GENERIC_GPIO_LIB
Abhay kumarfcf88202017-09-20 15:17:42 -070023 select HAVE_FSP_GOP
Lijian Zhao81096042017-05-02 18:54:44 -070024 select HAVE_HARD_RESET
25 select HAVE_INTEL_FIRMWARE
Lijian Zhaodcf99b02017-07-30 15:40:10 -070026 select HAVE_MONOTONIC_TIMER
Lijian Zhaof0eb9992017-09-14 14:51:12 -070027 select HAVE_SMI_HANDLER
Abhay Kumarb0c4cbb2017-10-12 11:33:01 -070028 select INTEL_GMA_ACPI
Abhay kumarfcf88202017-09-20 15:17:42 -070029 select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
Lijian Zhaoa5158492017-08-29 14:37:17 -070030 select IOAPIC
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070031 select MRC_SETTINGS_PROTECT
Pratik Prajapati01eda282017-08-17 21:09:45 -070032 select PARALLEL_MP
33 select PARALLEL_MP_AP_WORK
Lijian Zhao81096042017-05-02 18:54:44 -070034 select PLATFORM_USES_FSP2_0
Lijian Zhao8465a812017-07-11 12:33:22 -070035 select POSTCAR_CONSOLE
36 select POSTCAR_STAGE
Lijian Zhaodcf99b02017-07-30 15:40:10 -070037 select REG_SCRIPT
Lijian Zhaof0eb9992017-09-14 14:51:12 -070038 select RELOCATABLE_MODULES
Lijian Zhaoa77c68a2017-07-18 18:14:42 -070039 select RELOCATABLE_RAMSTAGE
Lijian Zhaof0eb9992017-09-14 14:51:12 -070040 select SMM_TSEG
Pratik Prajapati01eda282017-08-17 21:09:45 -070041 select SMP
Subrata Banikac1cd442018-02-06 15:25:27 +053042 select SOC_AHCI_PORT_IMPLEMENTED_INVERT
Lijian Zhao81096042017-05-02 18:54:44 -070043 select SOC_INTEL_COMMON
Lijian Zhao2b074d92017-08-17 14:25:24 -070044 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Lijian Zhao81096042017-05-02 18:54:44 -070045 select SOC_INTEL_COMMON_BLOCK
Lijian Zhao2b074d92017-08-17 14:25:24 -070046 select SOC_INTEL_COMMON_BLOCK_ACPI
Andrey Petrov3e2e0502017-06-05 13:22:24 -070047 select SOC_INTEL_COMMON_BLOCK_CPU
Pratik Prajapati01eda282017-08-17 21:09:45 -070048 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Lijian Zhao81096042017-05-02 18:54:44 -070049 select SOC_INTEL_COMMON_BLOCK_CSE
Lijian Zhao7b2d1ae2017-10-30 14:23:56 -070050 select SOC_INTEL_COMMON_BLOCK_DSP
Subrata Banik47569cf2017-10-12 17:59:02 +053051 select SOC_INTEL_COMMON_BLOCK_EBDA
Lijian Zhaodcf99b02017-07-30 15:40:10 -070052 select SOC_INTEL_COMMON_BLOCK_FAST_SPI
Andrey Petrovc854b492017-06-05 14:10:17 -070053 select SOC_INTEL_COMMON_BLOCK_GPIO
Subrata Banik75c6f4a2017-11-28 18:37:48 +053054 select SOC_INTEL_COMMON_BLOCK_GRAPHICS
Furquan Shaikha5bb7162017-12-20 11:09:04 -080055 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Lijian Zhaoa5158492017-08-29 14:37:17 -070056 select SOC_INTEL_COMMON_BLOCK_ITSS
Lijian Zhao9bb684a2017-10-30 17:03:06 -070057 select SOC_INTEL_COMMON_BLOCK_I2C
Lijian Zhaoa5158492017-08-29 14:37:17 -070058 select SOC_INTEL_COMMON_BLOCK_LPC
Lijian Zhaodcf99b02017-07-30 15:40:10 -070059 select SOC_INTEL_COMMON_BLOCK_LPSS
Lijian Zhao899f5ff2017-10-26 12:02:30 -070060 select SOC_INTEL_COMMON_BLOCK_P2SB
Lijian Zhaodcf99b02017-07-30 15:40:10 -070061 select SOC_INTEL_COMMON_BLOCK_PCR
Lijian Zhaob3dfcb82017-08-16 22:18:52 -070062 select SOC_INTEL_COMMON_BLOCK_PMC
Lijian Zhaodcf99b02017-07-30 15:40:10 -070063 select SOC_INTEL_COMMON_BLOCK_RTC
64 select SOC_INTEL_COMMON_BLOCK_SA
Subrata Banikac1cd442018-02-06 15:25:27 +053065 select SOC_INTEL_COMMON_BLOCK_SATA
Bora Guvendikd2c63652017-09-19 14:04:37 -070066 select SOC_INTEL_COMMON_BLOCK_SCS
Lijian Zhaodcf99b02017-07-30 15:40:10 -070067 select SOC_INTEL_COMMON_BLOCK_SMBUS
Brandon Breitensteinae154862017-08-01 11:32:06 -070068 select SOC_INTEL_COMMON_BLOCK_SMM
69 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik5a283ef2017-11-07 18:06:36 +053070 select SOC_INTEL_COMMON_BLOCK_SPI
Lijian Zhaodcf99b02017-07-30 15:40:10 -070071 select SOC_INTEL_COMMON_BLOCK_TIMER
72 select SOC_INTEL_COMMON_BLOCK_UART
Duncan Laurie2410cd92018-03-26 02:25:07 -070073 select SOC_INTEL_COMMON_BLOCK_XDCI
Lijian Zhao0e956f22017-10-22 18:30:39 -070074 select SOC_INTEL_COMMON_NHLT
Lijian Zhaodcf99b02017-07-30 15:40:10 -070075 select SOC_INTEL_COMMON_RESET
Lijian Zhaof0eb9992017-09-14 14:51:12 -070076 select SSE2
Lijian Zhaoacfc1492017-07-06 15:27:27 -070077 select SUPPORT_CPU_UCODE_IN_CBFS
Lijian Zhaodcf99b02017-07-30 15:40:10 -070078 select TSC_CONSTANT_RATE
79 select TSC_MONOTONIC_TIMER
80 select UDELAY_TSC
Subrata Banik74558812018-01-25 11:41:04 +053081 select UDK_2017_BINDING
Subrata Banika8733e32018-01-23 16:40:56 +053082 select DISPLAY_FSP_VERSION_INFO
Lijian Zhao81096042017-05-02 18:54:44 -070083
84config UART_DEBUG
85 bool "Enable UART debug port."
86 default y
87 select CONSOLE_SERIAL
88 select BOOTBLOCK_CONSOLE
89 select DRIVERS_UART
Lijian Zhaod37ebdd2017-08-30 20:54:16 -070090 select DRIVERS_UART_8250MEM_32
91 select NO_UART_ON_SUPERIO
Lijian Zhao81096042017-05-02 18:54:44 -070092
Subrata Banikce4c9ec2017-08-14 13:23:54 +053093config UART_FOR_CONSOLE
94 int "Index for LPSS UART port to use for console"
Lijian Zhao0c8237a2017-09-14 16:25:18 -070095 default 2 if DRIVERS_UART_8250MEM_32
Subrata Banikb045d4c2017-08-30 11:47:32 +053096 default 0
Subrata Banikce4c9ec2017-08-14 13:23:54 +053097 help
98 Index for LPSS UART port to use for console:
99 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
100
Lijian Zhao81096042017-05-02 18:54:44 -0700101config DCACHE_RAM_BASE
102 default 0xfef00000
103
104config DCACHE_RAM_SIZE
105 default 0x40000
106 help
107 The size of the cache-as-ram region required during bootblock
108 and/or romstage.
109
110config DCACHE_BSP_STACK_SIZE
111 hex
112 default 0x4000
113 help
114 The amount of anticipated stack usage in CAR by bootblock and
115 other stages.
116
Furquan Shaikhc0257dd2018-05-02 23:29:04 -0700117config IFD_CHIPSET
118 string
119 default "cnl"
120
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700121config IED_REGION_SIZE
122 hex
123 default 0x400000
124
John Zhao7492bcb2018-02-01 15:56:28 -0800125config HEAP_SIZE
126 hex
127 default 0x8000
128
Lijian Zhao0e956f22017-10-22 18:30:39 -0700129config NHLT_DMIC_1CH_16B
130 bool
131 depends on ACPI_NHLT
132 default n
133 help
134 Include DSP firmware settings for 1 channel 16B DMIC array.
135
136config NHLT_DMIC_2CH_16B
137 bool
138 depends on ACPI_NHLT
139 default n
140 help
141 Include DSP firmware settings for 2 channel 16B DMIC array.
142
143config NHLT_DMIC_4CH_16B
144 bool
145 depends on ACPI_NHLT
146 default n
147 help
148 Include DSP firmware settings for 4 channel 16B DMIC array.
149
150config NHLT_MAX98357
151 bool
152 depends on ACPI_NHLT
153 default n
154 help
155 Include DSP firmware settings for headset codec.
156
N, Harshapriya4a1ee4b2017-11-28 14:29:26 -0800157config NHLT_MAX98373
158 bool
159 depends on ACPI_NHLT
160 default n
161 help
162 Include DSP firmware settings for headset codec.
163
Lijian Zhao0e956f22017-10-22 18:30:39 -0700164config NHLT_DA7219
165 bool
166 depends on ACPI_NHLT
167 default n
168 help
169 Include DSP firmware settings for headset codec.
170
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700171config MAX_ROOT_PORTS
172 int
Lijian Zhaoc85890d2017-10-20 09:19:07 -0700173 default 16
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700174
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700175config SMM_TSEG_SIZE
176 hex
177 default 0x800000
178
Lijian Zhao81096042017-05-02 18:54:44 -0700179config PCR_BASE_ADDRESS
180 hex
181 default 0xfd000000
182 help
183 This option allows you to select MMIO Base Address of sideband bus.
184
Andrey Petrov3e2e0502017-06-05 13:22:24 -0700185config CPU_BCLK_MHZ
186 int
187 default 100
188
Nick Vaccaro780a1c42017-12-22 22:50:57 -0800189config SOC_INTEL_CANNONLAKE_LPDDR4_INIT
190 bool
191 default n
192
Aaron Durbin551e4be2018-04-10 09:24:54 -0600193config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Lijian Zhaof3885612017-11-09 15:01:33 -0800194 int
195 default 120
196
Chris Chingb8dc63b2017-12-06 14:26:15 -0700197config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
198 int
Lijian Zhaoe09ba472018-04-10 10:33:05 -0700199 default 133
Chris Chingb8dc63b2017-12-06 14:26:15 -0700200
Lijian Zhao32111172017-08-16 11:40:03 -0700201config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
202 int
203 default 3
204
Lijian Zhao8465a812017-07-11 12:33:22 -0700205# Clock divider parameters for 115200 baud rate
206config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
207 hex
208 default 0x30
209
210config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
211 hex
212 default 0xc35
213
Lijian Zhao6d7063c2017-08-29 17:26:48 -0700214config CHROMEOS
215 select CHROMEOS_RAMOOPS_DYNAMIC
216
217config VBOOT
218 select VBOOT_SEPARATE_VERSTAGE
219 select VBOOT_OPROM_MATTERS
220 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
221 select VBOOT_STARTS_IN_BOOTBLOCK
222 select VBOOT_VBNV_CMOS
223 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
224
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600225config C_ENV_BOOTBLOCK_SIZE
226 hex
Lijian Zhao031020e2017-12-15 12:58:07 -0800227 default 0x8000
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600228
John Zhao9b6384c2017-10-11 19:09:21 -0700229config STACK_SIZE
230 hex
231 default 0x2000
232
Subrata Banik9e3ba212018-01-08 15:28:26 +0530233choice
234 prompt "Cache-as-ram implementation"
235 default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS
236 default USE_CANNONLAKE_FSP_CAR
237 help
238 This option allows you to select how cache-as-ram (CAR) is set up.
239
240config USE_CANNONLAKE_CAR_NEM_ENHANCED
241 bool "Enhanced Non-evict mode"
242 select SOC_INTEL_COMMON_BLOCK_CAR
243 select INTEL_CAR_NEM_ENHANCED
244 help
245 A current limitation of NEM (Non-Evict mode) is that code and data
246 sizes are derived from the requirement to not write out any modified
247 cache line. With NEM, if there is no physical memory behind the
248 cached area, the modified data will be lost and NEM results will be
249 inconsistent. ENHANCED NEM guarantees that modified data is always
250 kept in cache while clean data is replaced.
251
252config USE_CANNONLAKE_FSP_CAR
253 bool "Use FSP CAR"
254 select FSP_CAR
255 help
256 Use FSP APIs to initialize and tear down the Cache-As-Ram.
257
258endchoice
259
Lijian Zhao81096042017-05-02 18:54:44 -0700260endif