soc/intel/xeon_sp/cpx: Work around FSP-M issues
Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.
TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB
Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 70703d0..88b0d5d 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -16,7 +16,6 @@
select UDK_2015_BINDING
select POSTCAR_CONSOLE
select POSTCAR_STAGE
- select FSP_USES_CB_STACK
config FSP_HEADER_PATH
string "Location of FSP headers"
@@ -40,11 +39,11 @@
# currently FSP hardcodes [0fe800000;fe930000] for its heap
config DCACHE_RAM_BASE
hex
- default 0xfe930000
+ default 0xfe9a0000
config DCACHE_RAM_SIZE
hex
- default 0xd0000
+ default 0x60000
config DCACHE_BSP_STACK_SIZE
hex