Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | ## This file is part of the coreboot project. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 3 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 4 | config NORTHBRIDGE_INTEL_SANDYBRIDGE |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 5 | bool |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 6 | select CACHE_MRC_SETTINGS |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 7 | select CPU_INTEL_MODEL_206AX |
| 8 | select HAVE_DEBUG_RAM_SETUP |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 9 | select INTEL_GMA_ACPI |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 10 | |
Nico Huber | 772a154 | 2019-05-10 16:48:14 +0200 | [diff] [blame] | 11 | if NORTHBRIDGE_INTEL_SANDYBRIDGE |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 12 | |
Patrick Rudolph | 1ee3dbc | 2020-02-28 13:11:13 +0100 | [diff] [blame] | 13 | config SANDYBRIDGE_VBOOT_IN_ROMSTAGE |
| 14 | bool |
| 15 | default n |
| 16 | help |
| 17 | Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE. |
| 18 | |
| 19 | config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK |
| 20 | depends on VBOOT |
| 21 | depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE |
| 22 | bool "Start verstage in bootblock" |
| 23 | default y |
| 24 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 25 | select VBOOT_SEPARATE_VERSTAGE |
| 26 | help |
| 27 | Sandy Bridge can either start verstage in a separate stage |
| 28 | right after the bootblock has run or it can start it |
| 29 | after romstage for compatibility reasons. |
| 30 | Sandy Bridge however uses a mrc.bin to initialize memory which |
| 31 | needs to be located at a fixed offset. Therefore even with |
| 32 | a separate verstage starting after the bootblock that same |
| 33 | binary is used meaning a jump is made from RW to the RO region |
| 34 | and back to the RW region after the binary is done. |
| 35 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 36 | config VBOOT |
Patrick Rudolph | 1ee3dbc | 2020-02-28 13:11:13 +0100 | [diff] [blame] | 37 | select VBOOT_MUST_REQUEST_DISPLAY |
| 38 | select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 39 | |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 40 | config USE_NATIVE_RAMINIT |
| 41 | bool "Use native raminit" |
| 42 | default y |
| 43 | help |
| 44 | Select if you want to use coreboot implementation of raminit rather than |
| 45 | System Agent/MRC.bin. You should answer Y. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 46 | |
Patrick Rudolph | b794a69 | 2017-08-08 13:13:51 +0200 | [diff] [blame] | 47 | config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES |
| 48 | bool "Ignore vendor programmed fuses that limit max. DRAM frequency" |
| 49 | default n |
| 50 | depends on USE_NATIVE_RAMINIT |
| 51 | help |
| 52 | Ignore the mainboard's vendor programmed fuses that might limit the |
| 53 | maximum DRAM frequency. By selecting this option the fuses will be |
| 54 | ignored and the only limits on DRAM frequency are set by RAM's SPD and |
| 55 | hard fuses in southbridge's clockgen. |
| 56 | Disabled by default as it might causes system instability. |
| 57 | Handle with care! |
| 58 | |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 59 | config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS |
| 60 | bool "Ignore XMP profile max DIMMs per channel" |
| 61 | default n |
| 62 | depends on USE_NATIVE_RAMINIT |
| 63 | help |
| 64 | Ignore the max DIMMs per channel restriciton defined in XMP profiles. |
| 65 | Disabled by default as it might cause system instability. |
| 66 | Handle with care! |
| 67 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 68 | config CBFS_SIZE |
| 69 | hex |
| 70 | default 0x100000 |
| 71 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 72 | config VGA_BIOS_ID |
| 73 | string |
| 74 | default "8086,0106" |
| 75 | |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 76 | config MMCONF_BASE_ADDRESS |
| 77 | hex |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 78 | default 0xf0000000 |
| 79 | help |
Arthur Heymans | 742a0e9 | 2018-01-29 16:34:46 +0100 | [diff] [blame] | 80 | The MRC blob requires it to be at 0xf0000000. |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 81 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 82 | config DCACHE_RAM_BASE |
| 83 | hex |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 84 | default 0xfefe0000 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 85 | |
Arthur Heymans | 67d59d1 | 2019-11-16 20:06:20 +0100 | [diff] [blame] | 86 | config DCACHE_BSP_STACK_SIZE |
| 87 | hex |
Arthur Heymans | 8d82109 | 2019-11-25 06:56:04 +0100 | [diff] [blame] | 88 | default 0x10000 |
| 89 | help |
| 90 | The amount of BSP stack anticipated in bootblock and |
| 91 | other stages. |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 92 | |
| 93 | if USE_NATIVE_RAMINIT |
| 94 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 95 | config DCACHE_RAM_SIZE |
| 96 | hex |
| 97 | default 0x20000 |
| 98 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 99 | config DCACHE_RAM_MRC_VAR_SIZE |
| 100 | hex |
| 101 | default 0x0 |
| 102 | |
| 103 | endif # USE_NATIVE_RAMINIT |
| 104 | |
| 105 | if !USE_NATIVE_RAMINIT |
| 106 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 107 | config DCACHE_RAM_SIZE |
| 108 | hex |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 109 | default 0x17000 |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 110 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 111 | config DCACHE_RAM_MRC_VAR_SIZE |
| 112 | hex |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 113 | default 0x9000 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 114 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 115 | config MRC_FILE |
| 116 | string "Intel System Agent path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 117 | default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 118 | help |
| 119 | The path and filename of the file to use as System Agent |
| 120 | binary. |
| 121 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 122 | endif # !USE_NATIVE_RAMINIT |
Kyösti Mälkki | 0306e6a | 2016-06-23 12:41:40 +0300 | [diff] [blame] | 123 | |
Nico Huber | 612a867 | 2019-02-19 19:11:29 +0100 | [diff] [blame] | 124 | config INTEL_GMA_BCLV_OFFSET |
| 125 | default 0x48254 |
| 126 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 127 | endif |