Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | a880257 | 2016-10-10 20:26:01 +0200 | [diff] [blame] | 16 | #define SYSTEM_TYPE 1 /* SERVER = 0, DESKTOP = 1, MOBILE = 2 */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 17 | |
Elyes HAOUAS | a880257 | 2016-10-10 20:26:01 +0200 | [diff] [blame] | 18 | /* used by incoherent_ht */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 19 | #define FAM10_SCAN_PCI_BUS 0 |
| 20 | #define FAM10_ALLOCATE_IO_RANGE 0 |
| 21 | |
| 22 | #include <stdint.h> |
| 23 | #include <string.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 28 | #include <cpu/x86/lapic.h> |
| 29 | #include <console/console.h> |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 30 | #include <timestamp.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 31 | #include <cpu/amd/model_10xxx_rev.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 32 | #include <lib.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 33 | #include <cpu/x86/lapic.h> |
Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 34 | #include <commonlib/loglevel.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <cpu/x86/bist.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 36 | #include <cpu/amd/mtrr.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 37 | #include <cpu/amd/car.h> |
| 38 | #include <southbridge/amd/sb800/smbus.h> |
| 39 | #include <northbridge/amd/amdfam10/raminit.h> |
| 40 | #include <northbridge/amd/amdht/ht_wrapper.h> |
| 41 | #include <cpu/amd/family_10h-family_15h/init_cpus.h> |
| 42 | #include <arch/early_variables.h> |
| 43 | #include <cbmem.h> |
Arthur Heymans | 6d1fdb3 | 2017-06-21 14:44:13 +0200 | [diff] [blame] | 44 | #include <southbridge/amd/rs780/rs780.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 45 | #include "southbridge/amd/sb800/early_setup.c" |
Patrick Georgi | c9a08dd | 2011-03-04 17:09:21 +0000 | [diff] [blame] | 46 | #include <spd.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 47 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 48 | #include "resourcemap.c" |
| 49 | #include "cpu/amd/quadcore/quadcore.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 50 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 51 | void activate_spd_rom(const struct mem_controller *ctrl); |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame^] | 52 | int spd_read_byte(unsigned int device, unsigned int address); |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 53 | extern struct sys_info sysinfo_car; |
| 54 | |
| 55 | void activate_spd_rom(const struct mem_controller *ctrl) |
| 56 | { |
| 57 | } |
| 58 | |
| 59 | int spd_read_byte(u32 device, u32 address) |
| 60 | { |
| 61 | return do_smbus_read_byte(SMBUS_IO_BASE, device, address); |
| 62 | } |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 63 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 64 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 65 | { |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 66 | struct sys_info *sysinfo = &sysinfo_car; |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 67 | static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; |
| 68 | u32 bsp_apicid = 0, val; |
| 69 | msr_t msr; |
| 70 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 71 | timestamp_init(timestamp_get()); |
| 72 | timestamp_add_now(TS_START_ROMSTAGE); |
| 73 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 74 | if (!cpu_init_detectedx && boot_cpu()) { |
| 75 | /* Nothing special needs to be done to find bus 0 */ |
| 76 | /* Allow the HT devices to be found */ |
| 77 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 78 | set_bsp_node_CHtExtNodeCfgEn(); |
| 79 | enumerate_ht_chain(); |
| 80 | |
| 81 | /* enable port80 decoding and southbridge poweron init */ |
| 82 | sb800_lpc_port80(); |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 83 | inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | post_code(0x30); |
| 87 | |
| 88 | if (bist == 0) { |
| 89 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ |
| 90 | /* All cores run this but the BSP(node0,core0) is the only core that returns. */ |
| 91 | } |
| 92 | |
| 93 | post_code(0x32); |
| 94 | |
| 95 | enable_rs780_dev8(); |
| 96 | sb800_lpc_init(); |
| 97 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 98 | console_init(); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 99 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 100 | |
| 101 | /* Halt if there was a built in self test failure */ |
| 102 | report_bist_failure(bist); |
| 103 | |
Elyes HAOUAS | a880257 | 2016-10-10 20:26:01 +0200 | [diff] [blame] | 104 | /* Load MPB */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 105 | val = cpuid_eax(1); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 106 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 107 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 108 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 109 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 110 | |
| 111 | /* Setup sysinfo defaults */ |
| 112 | set_sysinfo_in_ram(0); |
| 113 | |
| 114 | update_microcode(val); |
Kyösti Mälkki | f0a13ce | 2013-12-08 07:20:48 +0200 | [diff] [blame] | 115 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 116 | post_code(0x33); |
| 117 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 118 | cpuSetAMDMSR(0); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 119 | post_code(0x34); |
| 120 | |
| 121 | amd_ht_init(sysinfo); |
| 122 | post_code(0x35); |
| 123 | |
| 124 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 125 | finalize_node_setup(sysinfo); |
| 126 | |
| 127 | /* Setup any mainboard PCI settings etc. */ |
| 128 | setup_mb_resource_map(); |
| 129 | post_code(0x36); |
| 130 | |
| 131 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 132 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 133 | It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 134 | I think it could be done by putting the spinlock flag in the cache |
| 135 | of the BSP located right after sysinfo. |
| 136 | */ |
| 137 | wait_all_core0_started(); |
| 138 | |
Martin Roth | f95911a | 2017-06-24 21:45:13 -0600 | [diff] [blame] | 139 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 140 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 141 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 142 | start_other_cores(bsp_apicid); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 143 | post_code(0x37); |
| 144 | wait_all_other_cores_started(bsp_apicid); |
| 145 | #endif |
| 146 | |
| 147 | post_code(0x38); |
| 148 | |
| 149 | /* run _early_setup before soft-reset. */ |
| 150 | rs780_early_setup(); |
| 151 | sb800_early_setup(); |
| 152 | |
Martin Roth | f95911a | 2017-06-24 21:45:13 -0600 | [diff] [blame] | 153 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 154 | msr = rdmsr(0xc0010071); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 155 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 156 | |
| 157 | /* FIXME: The sb fid change may survive the warm reset and only |
| 158 | need to be done once.*/ |
| 159 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 160 | |
| 161 | post_code(0x39); |
| 162 | |
Elyes HAOUAS | a880257 | 2016-10-10 20:26:01 +0200 | [diff] [blame] | 163 | if (!warm_reset_detect(0)) { /* BSP is node 0 */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 164 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 165 | } else { |
Elyes HAOUAS | a880257 | 2016-10-10 20:26:01 +0200 | [diff] [blame] | 166 | init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | post_code(0x3A); |
| 170 | |
| 171 | /* show final fid and vid */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 172 | msr = rdmsr(0xc0010071); |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 174 | #endif |
| 175 | |
| 176 | rs780_htinit(); |
| 177 | |
| 178 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 179 | if (!warm_reset_detect(0)) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 180 | printk(BIOS_INFO, "...WARM RESET...\n\n\n"); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 181 | soft_reset(); |
Jonathan Neuschäfer | ec48c74 | 2017-09-29 02:45:31 +0200 | [diff] [blame] | 182 | die("After soft_reset - shouldn't see this message!!!\n"); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | post_code(0x3B); |
| 186 | |
| 187 | /* It's the time to set ctrl in sysinfo now; */ |
| 188 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
| 189 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 190 | |
| 191 | post_code(0x40); |
| 192 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 193 | timestamp_add_now(TS_BEFORE_INITRAM); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 195 | raminit_amdmct(sysinfo); |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 196 | timestamp_add_now(TS_AFTER_INITRAM); |
| 197 | |
Timothy Pearson | 86f4ca5 | 2015-03-13 13:27:58 -0500 | [diff] [blame] | 198 | cbmem_initialize_empty(); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 199 | post_code(0x41); |
| 200 | |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 201 | amdmct_cbmem_store_info(sysinfo); |
| 202 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 203 | sb800_before_pci_init(); |
| 204 | |
| 205 | post_code(0x42); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 206 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 207 | |
| 208 | /** |
| 209 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 210 | * Description: |
| 211 | * This routine is called every time a non-coherent chain is processed. |
| 212 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 213 | * swap list. The first part of the list controls the BUID assignment and the |
| 214 | * second part of the list provides the device to device linking. Device orientation |
| 215 | * can be detected automatically, or explicitly. See documentation for more details. |
| 216 | * |
| 217 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 218 | * based on each device's unit count. |
| 219 | * |
| 220 | * Parameters: |
Martin Roth | c3fde7e | 2014-12-29 22:13:37 -0700 | [diff] [blame] | 221 | * @param[in] node = The node on which this chain is located |
| 222 | * @param[in] link = The link on the host for this chain |
| 223 | * @param[out] List = supply a pointer to a list |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 224 | */ |
| 225 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 226 | { |
| 227 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 228 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 229 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 230 | *List = swaplist; |
| 231 | return 1; |
| 232 | } |
| 233 | |
| 234 | return 0; |
| 235 | } |