Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 3 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 4 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 5 | #include <cpu/x86/post_code.h> |
| 6 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 7 | .global bootblock_pre_c_entry |
| 8 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 9 | .code32 |
| 10 | _cache_as_ram_setup: |
| 11 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 12 | bootblock_pre_c_entry: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 13 | |
| 14 | cache_as_ram: |
| 15 | post_code(0x20) |
| 16 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 17 | /* Clear/disable fixed MTRRs */ |
| 18 | mov $fixed_mtrr_list_size, %ebx |
| 19 | xor %eax, %eax |
| 20 | xor %edx, %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 21 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 22 | clear_fixed_mtrr: |
| 23 | add $-2, %ebx |
| 24 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 25 | wrmsr |
| 26 | jnz clear_fixed_mtrr |
| 27 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 28 | /* Figure out how many MTRRs we have, and clear them out */ |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 29 | mov $MTRR_CAP_MSR, %ecx |
| 30 | rdmsr |
| 31 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 32 | mov $MTRR_PHYS_BASE(0), %ecx |
| 33 | xor %eax, %eax |
| 34 | xor %edx, %edx |
| 35 | |
| 36 | clear_var_mtrr: |
| 37 | wrmsr |
| 38 | inc %ecx |
| 39 | wrmsr |
| 40 | inc %ecx |
| 41 | dec %ebx |
| 42 | jnz clear_var_mtrr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 43 | post_code(0x21) |
| 44 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 45 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 46 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 47 | rdmsr |
| 48 | andl $(~0x00000cff), %eax |
| 49 | wrmsr |
| 50 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 51 | post_code(0x22) |
| 52 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 53 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 54 | movl $1, %eax |
| 55 | cpuid |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 56 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 57 | jz addrsize_set_high |
| 58 | movl $0x0f, %edx |
| 59 | |
| 60 | /* Preload high word of address mask (in %edx) for Variable |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 61 | MTRRs 0 and 1. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 62 | addrsize_set_high: |
| 63 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 64 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 65 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 66 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 67 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 68 | |
| 69 | post_code(0x2a) |
| 70 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 71 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 72 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 73 | movl $_car_mtrr_start, %eax |
| 74 | orl $MTRR_TYPE_WRBACK, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 75 | xorl %edx, %edx |
| 76 | wrmsr |
| 77 | |
| 78 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 79 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 80 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 81 | movl $_car_mtrr_mask, %eax |
| 82 | orl $MTRR_PHYS_MASK_VALID, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 83 | wrmsr |
| 84 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 85 | post_code(0x2b) |
| 86 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 87 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 88 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 89 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 90 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 91 | wrmsr |
| 92 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 93 | post_code(0x2c) |
| 94 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 95 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 96 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 97 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 98 | invd |
| 99 | movl %eax, %cr0 |
| 100 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 101 | /* Read then clear the CAR region. This will also fill up the cache. |
| 102 | * IMPORTANT: The read is mandatory. |
| 103 | */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 104 | cld |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 105 | movl $_car_mtrr_start, %edi |
| 106 | movl $_car_mtrr_size, %ecx |
| 107 | shr $2, %ecx |
| 108 | movl %ecx, %ebx |
| 109 | movl %edi, %esi |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 110 | rep lodsl |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 111 | movl %ebx, %ecx |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 112 | xorl %eax, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 113 | rep stosl |
| 114 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 115 | post_code(0x2d) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 116 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 117 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 118 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 119 | movl %eax, %cr0 |
| 120 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 121 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 122 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 123 | xorl %edx, %edx |
| 124 | /* |
| 125 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame] | 126 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 127 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 128 | movl $_program, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 129 | andl $_xip_mtrr_mask, %eax |
Kyösti Mälkki | dc4820b | 2016-07-21 19:51:01 +0300 | [diff] [blame] | 130 | orl $MTRR_TYPE_WRPROT, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 131 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 132 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 133 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame^] | 134 | movl $_xip_mtrr_mask, %eax |
| 135 | orl $MTRR_PHYS_MASK_VALID, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 136 | wrmsr |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 137 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 138 | post_code(0x2e) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 139 | /* Enable cache. */ |
| 140 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 141 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 142 | movl %eax, %cr0 |
| 143 | |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 144 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 145 | mov $_ecar_stack, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 146 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 147 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 148 | the pushes below. */ |
| 149 | andl $0xfffffff0, %esp |
| 150 | subl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 151 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 152 | /* push TSC and BIST to stack */ |
| 153 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 154 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 155 | movd %mm2, %eax |
| 156 | pushl %eax /* tsc[63:32] */ |
| 157 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 158 | pushl %eax /* tsc[31:0] */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 159 | |
| 160 | before_c_entry: |
| 161 | post_code(0x29) |
| 162 | call bootblock_c_entry_bist |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 163 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 164 | /* Should never see this postcode */ |
| 165 | post_code(POST_DEAD_CODE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 166 | |
| 167 | .Lhlt: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 168 | hlt |
| 169 | jmp .Lhlt |
| 170 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 171 | fixed_mtrr_list: |
| 172 | .word MTRR_FIX_64K_00000 |
| 173 | .word MTRR_FIX_16K_80000 |
| 174 | .word MTRR_FIX_16K_A0000 |
| 175 | .word MTRR_FIX_4K_C0000 |
| 176 | .word MTRR_FIX_4K_C8000 |
| 177 | .word MTRR_FIX_4K_D0000 |
| 178 | .word MTRR_FIX_4K_D8000 |
| 179 | .word MTRR_FIX_4K_E0000 |
| 180 | .word MTRR_FIX_4K_E8000 |
| 181 | .word MTRR_FIX_4K_F0000 |
| 182 | .word MTRR_FIX_4K_F8000 |
| 183 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 184 | |
| 185 | _cache_as_ram_setup_end: |