Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2008 coresystems GmbH |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 20 | * Foundation, Inc. |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 21 | */ |
| 22 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 23 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 24 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 25 | #include <cpu/x86/post_code.h> |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 26 | #include <cpu/x86/lapic_def.h> |
| 27 | |
| 28 | /* Macro to access Local APIC registers at default base. */ |
| 29 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 30 | #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 31 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 32 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 33 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 34 | |
| 35 | /* Save the BIST result. */ |
| 36 | movl %eax, %ebp |
| 37 | |
| 38 | cache_as_ram: |
| 39 | post_code(0x20) |
| 40 | |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 41 | movl $LAPIC_BASE_MSR, %ecx |
| 42 | rdmsr |
| 43 | andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax |
| 44 | jz ap_init |
| 45 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 46 | /* Zero out all fixed range and variable range MTRRs. |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 47 | * For hyper-threaded CPUs these are shared. |
| 48 | */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 49 | movl $mtrr_table, %esi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 50 | movl $((mtrr_table_end - mtrr_table) >> 1), %edi |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 51 | xorl %eax, %eax |
| 52 | xorl %edx, %edx |
| 53 | clear_mtrrs: |
| 54 | movw (%esi), %bx |
| 55 | movzx %bx, %ecx |
| 56 | wrmsr |
| 57 | add $2, %esi |
| 58 | dec %edi |
| 59 | jnz clear_mtrrs |
| 60 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 61 | post_code(0x21) |
| 62 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 63 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 64 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 65 | rdmsr |
| 66 | andl $(~0x00000cff), %eax |
| 67 | wrmsr |
| 68 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 69 | post_code(0x22) |
| 70 | |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 71 | /* Determine CPU_ADDR_BITS and load PHYSMASK high |
| 72 | * word to %edx. |
| 73 | */ |
| 74 | movl $0x80000000, %eax |
| 75 | cpuid |
| 76 | cmpl $0x80000008, %eax |
| 77 | jc addrsize_no_MSR |
| 78 | movl $0x80000008, %eax |
| 79 | cpuid |
| 80 | movb %al, %cl |
| 81 | sub $32, %cl |
| 82 | movl $1, %edx |
| 83 | shl %cl, %edx |
| 84 | subl $1, %edx |
| 85 | jmp addrsize_set_high |
| 86 | addrsize_no_MSR: |
| 87 | movl $1, %eax |
| 88 | cpuid |
| 89 | andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ |
| 90 | jz addrsize_set_high |
| 91 | movl $0x0f, %edx |
| 92 | |
| 93 | /* Preload high word of address mask (in %edx) for Variable |
| 94 | * MTRRs 0 and 1 and enable local apic at default base. |
| 95 | */ |
| 96 | addrsize_set_high: |
| 97 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 98 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 99 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 100 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 101 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 102 | movl $LAPIC_BASE_MSR, %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 103 | not %edx |
| 104 | movl %edx, %ebx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 105 | rdmsr |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 106 | andl %ebx, %edx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 107 | andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax |
| 108 | orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax |
| 109 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 110 | |
| 111 | bsp_init: |
| 112 | |
| 113 | post_code(0x23) |
| 114 | |
| 115 | /* Send INIT IPI to all excluding ourself. */ |
| 116 | movl LAPIC(ICR), %edi |
| 117 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 118 | 1: movl %eax, (%edi) |
| 119 | movl $0x30, %ecx |
| 120 | 2: pause |
| 121 | dec %ecx |
| 122 | jnz 2b |
| 123 | movl (%edi), %ecx |
| 124 | andl $LAPIC_ICR_BUSY, %ecx |
| 125 | jnz 1b |
| 126 | |
| 127 | post_code(0x24) |
Patrick Georgi | 819c7d4 | 2012-03-31 13:08:12 +0200 | [diff] [blame] | 128 | |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 129 | movl $1, %eax |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 130 | cpuid |
| 131 | btl $28, %edx |
| 132 | jnc sipi_complete |
| 133 | bswapl %ebx |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 134 | movzx %bh, %edi |
| 135 | cmpb $1, %bh |
| 136 | jbe sipi_complete /* only one LAPIC ID in package */ |
| 137 | |
| 138 | movl $0, %eax |
| 139 | cpuid |
| 140 | movb $1, %bl |
| 141 | cmpl $4, %eax |
| 142 | jb cores_counted |
| 143 | movl $4, %eax |
| 144 | movl $0, %ecx |
| 145 | cpuid |
| 146 | shr $26, %eax |
| 147 | movb %al, %bl |
| 148 | inc %bl |
| 149 | |
| 150 | cores_counted: |
| 151 | movl %edi, %eax |
| 152 | divb %bl |
| 153 | cmpb $1, %al |
| 154 | jbe sipi_complete /* only LAPIC ID of a core */ |
| 155 | |
| 156 | /* For a hyper-threading processor, cache must not be disabled |
| 157 | * on an AP on the same physical package with the BSP. |
| 158 | */ |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 159 | |
| 160 | hyper_threading_cpu: |
| 161 | |
| 162 | /* delay 10 ms */ |
| 163 | movl $10000, %ecx |
| 164 | 1: inb $0x80, %al |
| 165 | dec %ecx |
| 166 | jnz 1b |
| 167 | |
| 168 | post_code(0x25) |
| 169 | |
| 170 | /* Send Start IPI to all excluding ourself. */ |
| 171 | movl LAPIC(ICR), %edi |
| 172 | movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax |
| 173 | 1: movl %eax, (%edi) |
| 174 | movl $0x30, %ecx |
| 175 | 2: pause |
| 176 | dec %ecx |
| 177 | jnz 2b |
| 178 | movl (%edi), %ecx |
| 179 | andl $LAPIC_ICR_BUSY, %ecx |
| 180 | jnz 1b |
| 181 | |
| 182 | /* delay 250 us */ |
| 183 | movl $250, %ecx |
| 184 | 1: inb $0x80, %al |
| 185 | dec %ecx |
| 186 | jnz 1b |
| 187 | |
| 188 | post_code(0x26) |
| 189 | |
| 190 | /* Wait for sibling CPU to start. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 191 | 1: movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 192 | rdmsr |
| 193 | andl %eax, %eax |
| 194 | jnz sipi_complete |
| 195 | |
| 196 | movl $0x30, %ecx |
| 197 | 2: pause |
| 198 | dec %ecx |
| 199 | jnz 2b |
| 200 | jmp 1b |
| 201 | |
| 202 | |
| 203 | ap_init: |
| 204 | post_code(0x27) |
| 205 | |
| 206 | /* Do not disable cache (so BSP can enable it). */ |
| 207 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 208 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 209 | movl %eax, %cr0 |
| 210 | |
| 211 | post_code(0x28) |
| 212 | |
| 213 | /* MTRR registers are shared between HT siblings. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 214 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 215 | movl $(1<<12), %eax |
| 216 | xorl %edx, %edx |
| 217 | wrmsr |
| 218 | |
| 219 | post_code(0x29) |
| 220 | |
| 221 | ap_halt: |
| 222 | cli |
| 223 | 1: hlt |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 224 | jmp 1b |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 225 | |
| 226 | |
| 227 | |
| 228 | sipi_complete: |
| 229 | |
| 230 | post_code(0x2a) |
| 231 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 232 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 233 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 234 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 235 | xorl %edx, %edx |
| 236 | wrmsr |
| 237 | |
| 238 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 239 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 240 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 241 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 242 | wrmsr |
| 243 | |
| 244 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 245 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 246 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 247 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 248 | wrmsr |
| 249 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 250 | post_code(0x2b) |
| 251 | |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 252 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 253 | * |
| 254 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 255 | * 06_0x, 06_17, 06_1C |
| 256 | * |
| 257 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 258 | * Should this be set only after the system bus and/or memory |
| 259 | * controller can successfully handle write cycles? |
| 260 | */ |
| 261 | |
| 262 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 263 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 264 | |
| 265 | movl $1, %eax |
| 266 | cpuid |
| 267 | movl %eax, %ebx |
| 268 | andl $EAX_FAMILY(0x0f), %eax |
| 269 | cmpl $EAX_FAMILY(0x06), %eax |
| 270 | jne no_msr_11e |
| 271 | movl %ebx, %eax |
| 272 | andl $EAX_MODEL(0xff), %eax |
| 273 | cmpl $EAX_MODEL(0x17), %eax |
| 274 | je has_msr_11e |
| 275 | cmpl $EAX_MODEL(0x1c), %eax |
| 276 | je has_msr_11e |
| 277 | andl $EAX_MODEL(0xf0), %eax |
| 278 | cmpl $EAX_MODEL(0x00), %eax |
| 279 | jne no_msr_11e |
| 280 | has_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 281 | movl $0x11e, %ecx |
| 282 | rdmsr |
| 283 | orl $(1 << 8), %eax |
| 284 | wrmsr |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 285 | no_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 286 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 287 | post_code(0x2c) |
| 288 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 289 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 290 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 291 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 292 | invd |
| 293 | movl %eax, %cr0 |
| 294 | |
| 295 | /* Clear the cache memory reagion. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 296 | cld |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 297 | xorl %eax, %eax |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 298 | movl $CACHE_AS_RAM_BASE, %edi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 299 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 300 | rep stosl |
| 301 | |
| 302 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 303 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 304 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 305 | movl %eax, %cr0 |
| 306 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 307 | post_code(0x2d) |
| 308 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 309 | #if CONFIG_XIP_ROM_SIZE |
| 310 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 311 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 312 | xorl %edx, %edx |
| 313 | /* |
| 314 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 315 | * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 316 | */ |
| 317 | movl $copy_and_run, %eax |
| 318 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 319 | orl $MTRR_TYPE_WRBACK, %eax |
| 320 | wrmsr |
| 321 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 322 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 323 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 324 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 325 | wrmsr |
| 326 | #endif /* CONFIG_XIP_ROM_SIZE */ |
| 327 | |
| 328 | /* Enable cache. */ |
| 329 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 330 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 331 | movl %eax, %cr0 |
| 332 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 333 | post_code(0x2e) |
| 334 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 335 | /* Set up the stack pointer. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 336 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 337 | |
| 338 | /* Restore the BIST result. */ |
| 339 | movl %ebp, %eax |
| 340 | movl %esp, %ebp |
| 341 | pushl %eax |
| 342 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 343 | post_code(0x2f) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 344 | |
| 345 | /* Call romstage.c main function. */ |
| 346 | call main |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 347 | addl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 348 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 349 | post_code(0x30) |
| 350 | |
| 351 | /* Disable cache. */ |
| 352 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 353 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 354 | movl %eax, %cr0 |
| 355 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 356 | post_code(0x34) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 357 | |
| 358 | /* Disable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 359 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 360 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 361 | andl $(~MTRR_DEF_TYPE_EN), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 362 | wrmsr |
| 363 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 364 | post_code(0x35) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 365 | |
| 366 | invd |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 367 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 368 | post_code(0x36) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 369 | |
| 370 | /* Enable cache. */ |
| 371 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 372 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 373 | movl %eax, %cr0 |
| 374 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 375 | post_code(0x37) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 376 | |
| 377 | /* Disable cache. */ |
| 378 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 379 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 380 | movl %eax, %cr0 |
| 381 | |
| 382 | post_code(0x38) |
| 383 | |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 384 | /* Enable Write Back and Speculative Reads for low RAM. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 385 | movl $MTRR_PHYS_BASE(0), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 386 | movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax |
| 387 | xorl %edx, %edx |
| 388 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 389 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 390 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 391 | movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 392 | wrmsr |
| 393 | |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 394 | #if CACHE_ROM_SIZE |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 395 | /* Enable caching and Speculative Reads for Flash ROM device. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 396 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 397 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 398 | xorl %edx, %edx |
| 399 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 400 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 401 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 402 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 403 | wrmsr |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 404 | #endif |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 405 | |
| 406 | post_code(0x39) |
| 407 | |
| 408 | /* And enable cache again after setting MTRRs. */ |
| 409 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 410 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 411 | movl %eax, %cr0 |
| 412 | |
| 413 | post_code(0x3a) |
| 414 | |
| 415 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 416 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 417 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame^] | 418 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 419 | wrmsr |
| 420 | |
| 421 | post_code(0x3b) |
| 422 | |
| 423 | /* Invalidate the cache again. */ |
| 424 | invd |
| 425 | |
| 426 | post_code(0x3c) |
| 427 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 428 | __main: |
| 429 | post_code(POST_PREPARE_RAMSTAGE) |
| 430 | cld /* Clear direction flag. */ |
| 431 | |
Kyösti Mälkki | 1729cd8 | 2014-10-16 12:47:25 +0300 | [diff] [blame] | 432 | movl $CONFIG_RAMTOP, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 433 | movl %esp, %ebp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 434 | call copy_and_run |
| 435 | |
| 436 | .Lhlt: |
| 437 | post_code(POST_DEAD_CODE) |
| 438 | hlt |
| 439 | jmp .Lhlt |
| 440 | |
| 441 | mtrr_table: |
| 442 | /* Fixed MTRRs */ |
| 443 | .word 0x250, 0x258, 0x259 |
| 444 | .word 0x268, 0x269, 0x26A |
| 445 | .word 0x26B, 0x26C, 0x26D |
| 446 | .word 0x26E, 0x26F |
| 447 | /* Variable MTRRs */ |
| 448 | .word 0x200, 0x201, 0x202, 0x203 |
| 449 | .word 0x204, 0x205, 0x206, 0x207 |
| 450 | .word 0x208, 0x209, 0x20A, 0x20B |
| 451 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 452 | mtrr_table_end: |