Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2008 coresystems GmbH |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 20 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 21 | #include <cpu/x86/post_code.h> |
| 22 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 23 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 24 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 25 | |
| 26 | /* Save the BIST result. */ |
| 27 | movl %eax, %ebp |
| 28 | |
| 29 | cache_as_ram: |
| 30 | post_code(0x20) |
| 31 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame^] | 32 | /* Clear/disable fixed MTRRs */ |
| 33 | mov $fixed_mtrr_list_size, %ebx |
| 34 | xor %eax, %eax |
| 35 | xor %edx, %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 36 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame^] | 37 | clear_fixed_mtrr: |
| 38 | add $-2, %ebx |
| 39 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 40 | wrmsr |
| 41 | jnz clear_fixed_mtrr |
| 42 | |
| 43 | /* Figure put how many MTRRs we have, and clear them out */ |
| 44 | mov $MTRR_CAP_MSR, %ecx |
| 45 | rdmsr |
| 46 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 47 | mov $MTRR_PHYS_BASE(0), %ecx |
| 48 | xor %eax, %eax |
| 49 | xor %edx, %edx |
| 50 | |
| 51 | clear_var_mtrr: |
| 52 | wrmsr |
| 53 | inc %ecx |
| 54 | wrmsr |
| 55 | inc %ecx |
| 56 | dec %ebx |
| 57 | jnz clear_var_mtrr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 58 | post_code(0x21) |
| 59 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 60 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 61 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 62 | rdmsr |
| 63 | andl $(~0x00000cff), %eax |
| 64 | wrmsr |
| 65 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 66 | post_code(0x22) |
| 67 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 68 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 69 | movl $1, %eax |
| 70 | cpuid |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 71 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 72 | jz addrsize_set_high |
| 73 | movl $0x0f, %edx |
| 74 | |
| 75 | /* Preload high word of address mask (in %edx) for Variable |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 76 | MTRRs 0 and 1. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 77 | addrsize_set_high: |
| 78 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 79 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 80 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 81 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 82 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 83 | |
| 84 | post_code(0x2a) |
| 85 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 86 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 87 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 88 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 89 | xorl %edx, %edx |
| 90 | wrmsr |
| 91 | |
| 92 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 93 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 94 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 95 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 96 | wrmsr |
| 97 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 98 | post_code(0x2b) |
| 99 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 100 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 101 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 102 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 103 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 104 | wrmsr |
| 105 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 106 | post_code(0x2c) |
| 107 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 108 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 109 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 110 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 111 | invd |
| 112 | movl %eax, %cr0 |
| 113 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 114 | /* Read then clear the CAR region. This will also fill up the cache. |
| 115 | * IMPORTANT: The read is mandatory. |
| 116 | */ |
| 117 | movl $CACHE_AS_RAM_BASE, %esi |
| 118 | movl %esi, %edi |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 119 | cld |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 120 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 121 | rep lodsl |
| 122 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 123 | xorl %eax, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 124 | rep stosl |
| 125 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 126 | post_code(0x2d) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 127 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 128 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 129 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 130 | movl %eax, %cr0 |
| 131 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 132 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 133 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 134 | xorl %edx, %edx |
| 135 | /* |
| 136 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Paul Menzel | a8843de | 2017-06-05 12:33:23 +0200 | [diff] [blame] | 137 | * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 138 | */ |
| 139 | movl $copy_and_run, %eax |
| 140 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
Kyösti Mälkki | dc4820b | 2016-07-21 19:51:01 +0300 | [diff] [blame] | 141 | orl $MTRR_TYPE_WRPROT, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 142 | wrmsr |
| 143 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 144 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 145 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 146 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 147 | wrmsr |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 148 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 149 | post_code(0x2e) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 150 | /* Enable cache. */ |
| 151 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 152 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 153 | movl %eax, %cr0 |
| 154 | |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 155 | /* Setup the stack. */ |
| 156 | movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax |
| 157 | movl %eax, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 158 | |
| 159 | /* Restore the BIST result. */ |
| 160 | movl %ebp, %eax |
| 161 | movl %esp, %ebp |
| 162 | pushl %eax |
| 163 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 164 | before_romstage: |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 165 | post_code(0x2f) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 166 | /* Call romstage.c main function. */ |
Kyösti Mälkki | 408d392 | 2016-06-17 10:43:48 +0300 | [diff] [blame] | 167 | call romstage_main |
Kyösti Mälkki | 408d392 | 2016-06-17 10:43:48 +0300 | [diff] [blame] | 168 | /* Save return value from romstage_main. It contains the stack to use |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 169 | * after cache-as-ram is torn down. It also contains the information |
| 170 | * for setting up MTRRs. */ |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 171 | movl %eax, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 172 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 173 | post_code(0x30) |
| 174 | |
| 175 | /* Disable cache. */ |
| 176 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 177 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 178 | movl %eax, %cr0 |
| 179 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 180 | post_code(0x31) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 181 | |
| 182 | /* Disable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 183 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 184 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 185 | andl $(~MTRR_DEF_TYPE_EN), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 186 | wrmsr |
| 187 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 188 | post_code(0x32) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 189 | |
| 190 | invd |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 191 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 192 | post_code(0x33) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 193 | |
| 194 | /* Enable cache. */ |
| 195 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 196 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 197 | movl %eax, %cr0 |
| 198 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 199 | post_code(0x36) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 200 | |
| 201 | /* Disable cache. */ |
| 202 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 203 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 204 | movl %eax, %cr0 |
| 205 | |
| 206 | post_code(0x38) |
| 207 | |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 208 | /* Clear all of the variable MTRRs. */ |
| 209 | popl %ebx |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 210 | movl $MTRR_PHYS_BASE(0), %ecx |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 211 | clr %eax |
| 212 | clr %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 213 | |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 214 | 1: |
| 215 | testl %ebx, %ebx |
| 216 | jz 1f |
| 217 | wrmsr /* Write MTRR base. */ |
| 218 | inc %ecx |
| 219 | wrmsr /* Write MTRR mask. */ |
| 220 | inc %ecx |
| 221 | dec %ebx |
| 222 | jmp 1b |
| 223 | |
| 224 | 1: |
| 225 | /* Get number of MTRRs. */ |
| 226 | popl %ebx |
| 227 | movl $MTRR_PHYS_BASE(0), %ecx |
| 228 | 2: |
| 229 | testl %ebx, %ebx |
| 230 | jz 2f |
| 231 | |
| 232 | /* Low 32 bits of MTRR base. */ |
| 233 | popl %eax |
| 234 | /* Upper 32 bits of MTRR base. */ |
| 235 | popl %edx |
| 236 | /* Write MTRR base. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 237 | wrmsr |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 238 | inc %ecx |
| 239 | /* Low 32 bits of MTRR mask. */ |
| 240 | popl %eax |
| 241 | /* Upper 32 bits of MTRR mask. */ |
| 242 | popl %edx |
| 243 | /* Write MTRR mask. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 244 | wrmsr |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 245 | inc %ecx |
| 246 | |
| 247 | dec %ebx |
| 248 | jmp 2b |
| 249 | 2: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 250 | |
| 251 | post_code(0x39) |
| 252 | |
| 253 | /* And enable cache again after setting MTRRs. */ |
| 254 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 255 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 256 | movl %eax, %cr0 |
| 257 | |
| 258 | post_code(0x3a) |
| 259 | |
| 260 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 261 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 262 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 263 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 264 | wrmsr |
| 265 | |
| 266 | post_code(0x3b) |
| 267 | |
| 268 | /* Invalidate the cache again. */ |
| 269 | invd |
| 270 | |
| 271 | post_code(0x3c) |
| 272 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 273 | __main: |
| 274 | post_code(POST_PREPARE_RAMSTAGE) |
| 275 | cld /* Clear direction flag. */ |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 276 | call romstage_after_car |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 277 | |
| 278 | .Lhlt: |
| 279 | post_code(POST_DEAD_CODE) |
| 280 | hlt |
| 281 | jmp .Lhlt |
| 282 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame^] | 283 | fixed_mtrr_list: |
| 284 | .word MTRR_FIX_64K_00000 |
| 285 | .word MTRR_FIX_16K_80000 |
| 286 | .word MTRR_FIX_16K_A0000 |
| 287 | .word MTRR_FIX_4K_C0000 |
| 288 | .word MTRR_FIX_4K_C8000 |
| 289 | .word MTRR_FIX_4K_D0000 |
| 290 | .word MTRR_FIX_4K_D8000 |
| 291 | .word MTRR_FIX_4K_E0000 |
| 292 | .word MTRR_FIX_4K_E8000 |
| 293 | .word MTRR_FIX_4K_F0000 |
| 294 | .word MTRR_FIX_4K_F8000 |
| 295 | fixed_mtrr_list_size = . - fixed_mtrr_list |