Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2008 coresystems GmbH |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 20 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 21 | #include <cpu/x86/post_code.h> |
| 22 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 23 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 24 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 25 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 26 | .code32 |
| 27 | _cache_as_ram_setup: |
| 28 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 29 | /* Save the BIST result. */ |
| 30 | movl %eax, %ebp |
| 31 | |
| 32 | cache_as_ram: |
| 33 | post_code(0x20) |
| 34 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 35 | /* Clear/disable fixed MTRRs */ |
| 36 | mov $fixed_mtrr_list_size, %ebx |
| 37 | xor %eax, %eax |
| 38 | xor %edx, %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 39 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 40 | clear_fixed_mtrr: |
| 41 | add $-2, %ebx |
| 42 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 43 | wrmsr |
| 44 | jnz clear_fixed_mtrr |
| 45 | |
| 46 | /* Figure put how many MTRRs we have, and clear them out */ |
| 47 | mov $MTRR_CAP_MSR, %ecx |
| 48 | rdmsr |
| 49 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 50 | mov $MTRR_PHYS_BASE(0), %ecx |
| 51 | xor %eax, %eax |
| 52 | xor %edx, %edx |
| 53 | |
| 54 | clear_var_mtrr: |
| 55 | wrmsr |
| 56 | inc %ecx |
| 57 | wrmsr |
| 58 | inc %ecx |
| 59 | dec %ebx |
| 60 | jnz clear_var_mtrr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 61 | post_code(0x21) |
| 62 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 63 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 64 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 65 | rdmsr |
| 66 | andl $(~0x00000cff), %eax |
| 67 | wrmsr |
| 68 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 69 | post_code(0x22) |
| 70 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 71 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 72 | movl $1, %eax |
| 73 | cpuid |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 74 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 75 | jz addrsize_set_high |
| 76 | movl $0x0f, %edx |
| 77 | |
| 78 | /* Preload high word of address mask (in %edx) for Variable |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 79 | MTRRs 0 and 1. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 80 | addrsize_set_high: |
| 81 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 82 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 83 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 84 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 85 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 86 | |
| 87 | post_code(0x2a) |
| 88 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 89 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 90 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 91 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 92 | xorl %edx, %edx |
| 93 | wrmsr |
| 94 | |
| 95 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 96 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 97 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 98 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 99 | wrmsr |
| 100 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 101 | post_code(0x2b) |
| 102 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 103 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 104 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 105 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 106 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 107 | wrmsr |
| 108 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 109 | post_code(0x2c) |
| 110 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 111 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 112 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 113 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 114 | invd |
| 115 | movl %eax, %cr0 |
| 116 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 117 | /* Read then clear the CAR region. This will also fill up the cache. |
| 118 | * IMPORTANT: The read is mandatory. |
| 119 | */ |
| 120 | movl $CACHE_AS_RAM_BASE, %esi |
| 121 | movl %esi, %edi |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 122 | cld |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 123 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 124 | rep lodsl |
| 125 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 126 | xorl %eax, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 127 | rep stosl |
| 128 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 129 | post_code(0x2d) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 130 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 131 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 132 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 133 | movl %eax, %cr0 |
| 134 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 135 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 136 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 137 | xorl %edx, %edx |
| 138 | /* |
| 139 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame^] | 140 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 141 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 142 | movl $_program, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 143 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
Kyösti Mälkki | dc4820b | 2016-07-21 19:51:01 +0300 | [diff] [blame] | 144 | orl $MTRR_TYPE_WRPROT, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 145 | wrmsr |
| 146 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 147 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 148 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 149 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 150 | wrmsr |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 151 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 152 | post_code(0x2e) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 153 | /* Enable cache. */ |
| 154 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 155 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 156 | movl %eax, %cr0 |
| 157 | |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 158 | /* Setup the stack. */ |
| 159 | movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax |
| 160 | movl %eax, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 161 | |
| 162 | /* Restore the BIST result. */ |
| 163 | movl %ebp, %eax |
| 164 | movl %esp, %ebp |
| 165 | pushl %eax |
| 166 | |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 167 | before_romstage: |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 168 | post_code(0x2f) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 169 | /* Call romstage.c main function. */ |
Kyösti Mälkki | 408d392 | 2016-06-17 10:43:48 +0300 | [diff] [blame] | 170 | call romstage_main |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 171 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 172 | /* Should never see this postcode */ |
| 173 | post_code(POST_DEAD_CODE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 174 | |
| 175 | .Lhlt: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 176 | hlt |
| 177 | jmp .Lhlt |
| 178 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 179 | fixed_mtrr_list: |
| 180 | .word MTRR_FIX_64K_00000 |
| 181 | .word MTRR_FIX_16K_80000 |
| 182 | .word MTRR_FIX_16K_A0000 |
| 183 | .word MTRR_FIX_4K_C0000 |
| 184 | .word MTRR_FIX_4K_C8000 |
| 185 | .word MTRR_FIX_4K_D0000 |
| 186 | .word MTRR_FIX_4K_D8000 |
| 187 | .word MTRR_FIX_4K_E0000 |
| 188 | .word MTRR_FIX_4K_E8000 |
| 189 | .word MTRR_FIX_4K_F0000 |
| 190 | .word MTRR_FIX_4K_F8000 |
| 191 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 192 | |
| 193 | _cache_as_ram_setup_end: |