Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Michał Żygowski | f65c1e4 | 2019-12-01 18:14:39 +0100 | [diff] [blame] | 5 | #include <amdblocks/biosram.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 7 | #include <arch/hpet.h> |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Felix Held | a8da070 | 2023-06-05 21:19:27 +0200 | [diff] [blame] | 9 | #include <arch/vga.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
| 11 | #include <acpi/acpigen.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 12 | #include <cbmem.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 13 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 14 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 15 | #include <cpu/x86/lapic_def.h> |
Marshall Dawson | f82aa10 | 2017-09-20 18:01:41 -0600 | [diff] [blame] | 16 | #include <cpu/x86/msr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 20 | #include <amdblocks/agesawrapper.h> |
| 21 | #include <amdblocks/agesawrapper_call.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 22 | #include <amdblocks/ioapic.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 23 | #include <agesa_headers.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 24 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 25 | #include <soc/northbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 27 | #include <soc/iomap.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 28 | #include <stdint.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | #include <string.h> |
| 30 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 31 | #include "chip.h" |
| 32 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 33 | static void read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 34 | { |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 35 | unsigned int idx = 0; |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 36 | |
Felix Held | af17f0b | 2022-03-02 23:36:55 +0100 | [diff] [blame] | 37 | /* The northbridge has no PCI BARs implemented, so there's no need to call |
| 38 | pci_dev_read_resources for it */ |
| 39 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 40 | /* |
| 41 | * This MMCONF resource must be reserved in the PCI domain. |
| 42 | * It is not honored by the coreboot resource allocator if it is in |
| 43 | * the CPU_CLUSTER. |
| 44 | */ |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 45 | mmconf_resource(dev, idx++); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 46 | } |
| 47 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 48 | /** |
| 49 | * I tried to reuse the resource allocation code in set_resource() |
| 50 | * but it is too difficult to deal with the resource allocation magic. |
| 51 | */ |
| 52 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 53 | static void create_vga_resource(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 54 | { |
| 55 | struct bus *link; |
| 56 | |
| 57 | /* find out which link the VGA card is connected, |
| 58 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 59 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 60 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 61 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 62 | |
| 63 | /* no VGA card installed */ |
| 64 | if (link == NULL) |
| 65 | return; |
| 66 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 67 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 68 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 69 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 70 | } |
| 71 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 72 | static void set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 73 | { |
| 74 | struct bus *bus; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 75 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 76 | /* do we need this? */ |
| 77 | create_vga_resource(dev); |
| 78 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 79 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 80 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 81 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static void northbridge_init(struct device *dev) |
| 85 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 86 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 87 | } |
| 88 | |
Felix Held | 8cab80c | 2023-05-05 15:20:15 +0200 | [diff] [blame] | 89 | /* Used by \_SB.PCI0._CRS */ |
| 90 | static void acpi_fill_root_complex_tom(const struct device *device) |
| 91 | { |
| 92 | const char *scope; |
| 93 | |
| 94 | assert(device); |
| 95 | |
| 96 | scope = acpi_device_scope(device); |
| 97 | assert(scope); |
| 98 | acpigen_write_scope(scope); |
| 99 | |
| 100 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 101 | |
| 102 | /* |
| 103 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 104 | * here. |
| 105 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 106 | * slide 22ff. |
| 107 | * Shift value right by 20 bit to make it fit into 32bit, |
| 108 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 109 | */ |
| 110 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
| 111 | acpigen_pop_len(); |
| 112 | } |
| 113 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 114 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 115 | { |
| 116 | void *addr, *current; |
| 117 | |
| 118 | /* Skip the HEST header. */ |
| 119 | current = (void *)(hest + 1); |
| 120 | |
| 121 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 122 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 123 | current += acpi_create_hest_error_source(hest, current, 0, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 124 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 125 | |
| 126 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 127 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 128 | current += acpi_create_hest_error_source(hest, current, 1, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 129 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 130 | |
| 131 | return (unsigned long)current; |
| 132 | } |
| 133 | |
Felix Held | 1b410d9 | 2024-01-26 14:05:58 +0100 | [diff] [blame] | 134 | static unsigned long soc_acpi_write_tables(const struct device *device, |
| 135 | unsigned long current, |
| 136 | acpi_rsdp_t *rsdp) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 137 | { |
| 138 | acpi_srat_t *srat; |
| 139 | acpi_slit_t *slit; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 140 | acpi_header_t *alib; |
| 141 | acpi_header_t *ivrs; |
| 142 | acpi_hest_t *hest; |
| 143 | |
| 144 | /* HEST */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 145 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | hest = (acpi_hest_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 147 | acpi_write_hest(hest, acpi_fill_hest); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 148 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 149 | current += hest->header.length; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 150 | |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 151 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 152 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 153 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 154 | if (ivrs != NULL) { |
| 155 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 156 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 157 | current += ivrs->length; |
| 158 | acpi_add_table(rsdp, ivrs); |
| 159 | } else { |
| 160 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 161 | } |
| 162 | |
| 163 | /* SRAT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 164 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 165 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 166 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 167 | if (srat != NULL) { |
| 168 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 169 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 170 | current += srat->header.length; |
| 171 | acpi_add_table(rsdp, srat); |
| 172 | } else { |
| 173 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 174 | } |
| 175 | |
| 176 | /* SLIT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 177 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 178 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 179 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 180 | if (slit != NULL) { |
| 181 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 182 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 183 | current += slit->header.length; |
| 184 | acpi_add_table(rsdp, slit); |
| 185 | } else { |
| 186 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 187 | } |
| 188 | |
| 189 | /* ALIB */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 190 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 192 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 193 | if (alib != NULL) { |
| 194 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 195 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 196 | current += alib->length; |
| 197 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 198 | } else { |
| 199 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 200 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 201 | } |
| 202 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 203 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 204 | return current; |
| 205 | } |
| 206 | |
Felix Held | 26651c8 | 2022-10-13 16:12:40 +0200 | [diff] [blame] | 207 | struct device_operations stoneyridge_northbridge_operations = { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 208 | .read_resources = read_resources, |
| 209 | .set_resources = set_resources, |
| 210 | .enable_resources = pci_dev_enable_resources, |
| 211 | .init = northbridge_init, |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 212 | .acpi_fill_ssdt = acpi_fill_root_complex_tom, |
Felix Held | 1b410d9 | 2024-01-26 14:05:58 +0100 | [diff] [blame] | 213 | .write_acpi_tables = soc_acpi_write_tables, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 214 | }; |
| 215 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 216 | /* |
| 217 | * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, |
| 218 | * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining |
| 219 | * MMIO to posted. Route all I/O to the southbridge. |
| 220 | */ |
| 221 | void amd_initcpuio(void) |
| 222 | { |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 223 | uintptr_t topmem = get_top_of_mem_below_4gb(); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 224 | uintptr_t base, limit; |
| 225 | |
| 226 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 227 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
| 228 | |
| 229 | /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ |
| 230 | base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; |
Kyösti Mälkki | dea42e0 | 2021-05-31 20:26:16 +0300 | [diff] [blame] | 231 | limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 232 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); |
| 233 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |
| 234 | |
| 235 | /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ |
| 236 | base = (topmem >> 8) | MMIO_WE | MMIO_RE; |
| 237 | limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; |
| 238 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); |
| 239 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); |
| 240 | |
| 241 | /* Route all I/O downstream */ |
| 242 | base = 0 | IO_WE | IO_RE; |
| 243 | limit = ALIGN_DOWN(0xffff, 4 * KiB); |
| 244 | pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); |
| 245 | pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); |
| 246 | } |
| 247 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 248 | void fam15_finalize(void *chip_info) |
| 249 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 250 | u32 value; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 251 | |
| 252 | /* TODO: move IOAPIC code to dsdt.asl */ |
| 253 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); |
| 254 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 255 | |
| 256 | /* disable No Snoop */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 257 | value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); |
Richard Spiegel | 3d34ae3 | 2018-04-13 13:20:08 -0700 | [diff] [blame] | 258 | value &= ~HDA_NO_SNOOP_EN; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 259 | pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 260 | } |
| 261 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 262 | void domain_enable_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 263 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 264 | /* Must be called after PCI enumeration and resource allocation */ |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 265 | if (!acpi_is_wakeup_s3()) |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 266 | do_agesawrapper(AMD_INIT_MID, "amdinitmid"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 267 | } |
| 268 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 269 | void domain_read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 270 | { |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 271 | uint64_t uma_base = get_uma_base(); |
| 272 | uint32_t uma_size = get_uma_size(); |
| 273 | uint32_t mem_useable = (uintptr_t)cbmem_top(); |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 274 | uint32_t tom = get_top_of_mem_below_4gb(); |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 275 | uint64_t high_tom = get_top_of_mem_above_4gb(); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 276 | uint64_t high_mem_useable; |
| 277 | int idx = 0x10; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 278 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 279 | pci_domain_read_resources(dev); |
| 280 | |
Felix Held | d7ad140 | 2023-06-05 15:30:10 +0200 | [diff] [blame] | 281 | fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
| 282 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 283 | /* 0x0 -> 0x9ffff */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 284 | ram_range(dev, idx++, 0, 0xa0000); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 285 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 286 | /* 0xa0000 -> 0xbffff: legacy VGA */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 287 | mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 288 | |
| 289 | /* 0xc0000 -> 0xfffff: Option ROM */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 290 | reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 291 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 292 | /* |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 293 | * 0x100000 (1MiB) -> low top usable RAM |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 294 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 295 | */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 296 | ram_from_to(dev, idx++, 1 * MiB, mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 297 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 298 | /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 299 | reserved_ram_from_to(dev, idx++, mem_useable, tom); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 300 | |
Felix Held | 5913a54 | 2024-01-09 16:59:37 +0100 | [diff] [blame] | 301 | /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT |
| 302 | code can find this resource */ |
| 303 | mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000); |
| 304 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 305 | /* If there is memory above 4GiB */ |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 306 | if (high_tom >> 32) { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 307 | /* 4GiB -> high top usable */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 308 | if (uma_base >= (4ull * GiB)) |
| 309 | high_mem_useable = uma_base; |
| 310 | else |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 311 | high_mem_useable = high_tom; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 312 | |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 313 | ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 314 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 315 | /* High top usable RAM -> high top RAM */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 316 | if (uma_base >= (4ull * GiB)) { |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 317 | reserved_ram_range(dev, idx++, uma_base, uma_size); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 318 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 319 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 320 | } |
| 321 | |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 322 | __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } |
| 323 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 324 | void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) |
| 325 | { |
Felix Held | 727ee667 | 2023-12-20 22:47:03 +0100 | [diff] [blame] | 326 | params->IommuSupport = is_dev_enabled(DEV_PTR(iommu)); |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 327 | set_board_env_params(params); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | void SetNbMidParams(GNB_MID_CONFIGURATION *params) |
| 331 | { |
| 332 | /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ |
| 333 | params->iGpuVgaMode = 0; |
| 334 | params->GnbIoapicAddress = IO_APIC2_ADDR; |
| 335 | } |