blob: cb09d237506a22e681dd42712e24a869b1676321 [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001config CPU_INTEL_MODEL_206AX
2 bool
3
4config CPU_INTEL_MODEL_306AX
5 bool
6
7if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
8
9config CPU_SPECIFIC_OPTIONS
10 def_bool y
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070011 select ARCH_BOOTBLOCK_X86_32
Stefan Reinauer77b16552015-01-14 19:51:47 +010012 select ARCH_VERSTAGE_X86_32
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070013 select ARCH_ROMSTAGE_X86_32
14 select ARCH_RAMSTAGE_X86_32
Stefan Reinauer5c554632012-04-04 00:09:50 +020015 select SMP
16 select SSE2
Patrick Rudolphb9959e22017-06-06 10:44:29 +020017 select UDELAY_TSC
18 select TSC_CONSTANT_RATE
19 select TSC_MONOTONIC_TIMER
Stefan Reinauer5c554632012-04-04 00:09:50 +020020 select SMM_TSEG
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060021 select SUPPORT_CPU_UCODE_IN_CBFS
Sven Schnelle51676b12012-07-29 19:18:03 +020022 #select AP_IN_SIPI_WAIT
Stefan Reinauer0db68202012-08-07 14:44:51 -070023 select TSC_SYNC_MFENCE
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060024 select CPU_INTEL_COMMON
Arthur Heymans67031a52018-02-05 19:08:03 +010025 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymansedbf5d92018-01-25 20:03:42 +010026 select PARALLEL_MP
Stefan Reinauer5c554632012-04-04 00:09:50 +020027
28config BOOTBLOCK_CPU_INIT
29 string
30 default "cpu/intel/model_206ax/bootblock.c"
31
Kyösti Mälkkic13d65c2016-11-18 19:03:29 +020032config XIP_ROM_SIZE
33 hex
34 default 0x20000 if USE_NATIVE_RAMINIT
35
Stefan Reinauer5c554632012-04-04 00:09:50 +020036config SMM_TSEG_SIZE
37 hex
38 default 0x800000
39
Arthur Heymans67031a52018-02-05 19:08:03 +010040config SMM_RESERVED_SIZE
41 hex
42 default 0x100000
43
44# Intel Enhanced Debug region must be 4MB
45config IED_REGION_SIZE
46 hex
47 default 0x400000
48
Vadim Bendebury999e94c2012-06-19 04:20:20 +000049endif