Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 17 | #include <bootmode.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 18 | #include <device/mmio.h> |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 19 | #include <delay.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 20 | #include <arch/io.h> |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 24 | #include <device/pci_ids.h> |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 26 | #include <edid.h> |
| 27 | #include <drivers/intel/gma/edid.h> |
| 28 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 29 | #include <drivers/intel/gma/opregion.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 30 | #include <string.h> |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 31 | #include <pc80/vga.h> |
| 32 | #include <pc80/vga_io.h> |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 33 | #include <commonlib/helpers.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 34 | #include <cbmem.h> |
| 35 | #include <southbridge/intel/i82801gx/nvs.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 36 | #include <types.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 37 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 38 | #include "i945.h" |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 39 | #include "chip.h" |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 40 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 41 | #define GDRST 0xc0 |
Arthur Heymans | c057a061 | 2016-10-22 14:16:48 +0200 | [diff] [blame] | 42 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 43 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 44 | #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
| 45 | #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
| 46 | #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
Elyes HAOUAS | 8868fc6 | 2017-06-28 20:41:53 +0200 | [diff] [blame] | 47 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 48 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 49 | |
Elyes HAOUAS | 692e7df | 2017-06-28 20:44:41 +0200 | [diff] [blame] | 50 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 51 | |
| 52 | #define PGETBL_CTL 0x2020 |
| 53 | #define PGETBL_ENABLED 0x00000001 |
| 54 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 55 | #define BASE_FREQUENCY 100000 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 56 | |
Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 57 | #define DEFAULT_BLC_PWM 180 |
| 58 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 59 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 60 | { |
| 61 | const global_nvs_t *gnvs_ptr = gnvs; |
| 62 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 63 | } |
| 64 | |
| 65 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 66 | { |
| 67 | global_nvs_t *gnvs_ptr = gnvs; |
| 68 | if (gnvs_ptr) |
| 69 | gnvs_ptr->aslb = aslb; |
| 70 | } |
| 71 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 72 | static int gtt_setup(u8 *mmiobase) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 73 | { |
| 74 | unsigned long PGETBL_save; |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 75 | unsigned long tom; // top of memory |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 76 | |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 77 | /* |
| 78 | * The Video BIOS places the GTT right below top of memory. |
Denis 'GNUtoo' Carikli | 16110e7 | 2014-10-14 07:33:53 +0200 | [diff] [blame] | 79 | */ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 80 | tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24; |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 81 | PGETBL_save = tom - 256 * KiB; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 82 | PGETBL_save |= PGETBL_ENABLED; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 83 | PGETBL_save |= 2; /* set GTT to 256kb */ |
| 84 | |
| 85 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 86 | |
| 87 | write32(mmiobase + PGETBL_CTL, PGETBL_save); |
| 88 | |
| 89 | /* verify */ |
| 90 | if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { |
| 91 | printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); |
| 92 | } else { |
| 93 | printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); |
| 94 | return 1; |
| 95 | } |
| 96 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 101 | static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 102 | unsigned int pphysbase, unsigned int piobase, |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 103 | u8 *mmiobase, unsigned int pgfx) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 104 | { |
| 105 | struct edid edid; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 106 | struct edid_mode *mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 107 | u8 edid_data[128]; |
| 108 | unsigned long temp; |
| 109 | int hpolarity, vpolarity; |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 110 | u32 smallest_err = 0xffffffff; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 111 | u32 target_frequency; |
| 112 | u32 pixel_p1 = 1; |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 113 | u32 pixel_p2; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 114 | u32 pixel_n = 1; |
| 115 | u32 pixel_m1 = 1; |
| 116 | u32 pixel_m2 = 1; |
| 117 | u32 hactive, vactive, right_border, bottom_border; |
| 118 | u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; |
| 119 | u32 i, j; |
| 120 | u32 uma_size; |
| 121 | u16 reg16; |
| 122 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 123 | printk(BIOS_SPEW, |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 124 | "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 125 | (void *)pgfx, mmiobase, piobase, pphysbase); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 126 | |
Arthur Heymans | 8da2286 | 2017-08-06 15:56:30 +0200 | [diff] [blame] | 127 | intel_gmbus_read_edid(mmiobase + GMBUS0, GMBUS_PORT_PANEL, 0x50, |
| 128 | edid_data, sizeof(edid_data)); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 129 | decode_edid(edid_data, sizeof(edid_data), &edid); |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 130 | mode = &edid.mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 131 | |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 132 | hpolarity = (mode->phsync == '-'); |
| 133 | vpolarity = (mode->pvsync == '-'); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 134 | hactive = edid.x_resolution; |
| 135 | vactive = edid.y_resolution; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 136 | right_border = mode->hborder; |
| 137 | bottom_border = mode->vborder; |
| 138 | vblank = mode->vbl; |
| 139 | hblank = mode->hbl; |
| 140 | vsync = mode->vspw; |
| 141 | hsync = mode->hspw; |
| 142 | hfront_porch = mode->hso; |
| 143 | vfront_porch = mode->vso; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 144 | |
| 145 | for (i = 0; i < 2; i++) |
| 146 | for (j = 0; j < 0x100; j++) |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 147 | /* R = j, G = j, B = j. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 148 | write32(mmiobase + PALETTE(i) + 4 * j, 0x10101 * j); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 149 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 150 | write32(mmiobase + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 151 | | (read32(mmiobase + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 152 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 153 | write32(mmiobase + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 154 | /* Clean registers. */ |
| 155 | for (i = 0; i < 0x20; i += 4) |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 156 | write32(mmiobase + RENDER_RING_BASE + i, 0); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 157 | for (i = 0; i < 0x20; i += 4) |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 158 | write32(mmiobase + FENCE_REG_965_0 + i, 0); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 159 | |
| 160 | /* Disable VGA. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 161 | write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 162 | |
| 163 | /* Disable pipes. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 164 | write32(mmiobase + PIPECONF(0), 0); |
| 165 | write32(mmiobase + PIPECONF(1), 0); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 166 | |
| 167 | /* Init PRB0. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 168 | write32(mmiobase + HWS_PGA, 0x352d2000); |
| 169 | write32(mmiobase + PRB0_CTL, 0); |
| 170 | write32(mmiobase + PRB0_HEAD, 0); |
| 171 | write32(mmiobase + PRB0_TAIL, 0); |
| 172 | write32(mmiobase + PRB0_START, 0); |
| 173 | write32(mmiobase + PRB0_CTL, 0x0001f001); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 174 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 175 | write32(mmiobase + D_STATE, DSTATE_PLL_D3_OFF |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 176 | | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 177 | write32(mmiobase + ECOSKPD, 0x00010000); |
| 178 | write32(mmiobase + HWSTAM, 0xeffe); |
| 179 | write32(mmiobase + PORT_HOTPLUG_EN, conf->gpu_hotplug); |
| 180 | write32(mmiobase + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 181 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 182 | /* p2 divisor must 7 for dual channel LVDS */ |
| 183 | /* and 14 for single channel LVDS */ |
| 184 | pixel_p2 = mode->lvds_dual_channel ? 7 : 14; |
| 185 | target_frequency = mode->pixel_clock; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 186 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 187 | /* Find suitable divisors, m1, m2, p1, n. */ |
| 188 | /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ |
| 189 | /* should be closest to target frequency as possible */ |
| 190 | u32 candn, candm1, candm2, candp1; |
| 191 | for (candm1 = 8; candm1 <= 18; candm1++) { |
| 192 | for (candm2 = 3; candm2 <= 7; candm2++) { |
| 193 | for (candn = 1; candn <= 6; candn++) { |
| 194 | for (candp1 = 1; candp1 <= 8; candp1++) { |
| 195 | u32 m = 5 * (candm1 + 2) + (candm2 + 2); |
| 196 | u32 p = candp1 * pixel_p2; |
| 197 | u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); |
| 198 | u32 dot = DIV_ROUND_CLOSEST(vco, p); |
Arthur Heymans | 75f9131 | 2016-10-12 01:04:28 +0200 | [diff] [blame] | 199 | u32 this_err = MAX(dot, target_frequency) - |
| 200 | MIN(dot, target_frequency); |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 201 | if ((m < 70) || (m > 120)) |
| 202 | continue; |
| 203 | if (this_err < smallest_err) { |
| 204 | smallest_err = this_err; |
| 205 | pixel_n = candn; |
| 206 | pixel_m1 = candm1; |
| 207 | pixel_m2 = candm2; |
| 208 | pixel_p1 = candp1; |
| 209 | } |
| 210 | } |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 211 | } |
| 212 | } |
| 213 | } |
| 214 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 215 | if (smallest_err == 0xffffffff) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 216 | printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 217 | return -1; |
| 218 | } |
| 219 | |
| 220 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 221 | hactive, vactive); |
| 222 | printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); |
| 223 | printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); |
| 224 | printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); |
| 225 | printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); |
| 226 | printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock |
| 227 | ? "Spread spectrum clock\n" |
| 228 | : "DREF clock\n")); |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 229 | printk(BIOS_DEBUG, (mode->lvds_dual_channel |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 230 | ? "Dual channel\n" |
| 231 | : "Single channel\n")); |
| 232 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 233 | hpolarity, vpolarity); |
| 234 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", |
| 235 | pixel_n, pixel_m1, pixel_m2, pixel_p1); |
| 236 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 237 | BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / |
| 238 | (pixel_n + 2) / (pixel_p1 * pixel_p2)); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 239 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 240 | printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ? |
Paul Menzel | bcf9a0a | 2018-02-18 10:05:53 +0100 | [diff] [blame] | 241 | "Linear framebuffer" : "text"); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 242 | if (CONFIG(LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 243 | /* Disable panel fitter (we're in native resolution). */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 244 | write32(mmiobase + PF_CTL(0), 0); |
| 245 | write32(mmiobase + PF_WIN_SZ(0), 0); |
| 246 | write32(mmiobase + PF_WIN_POS(0), 0); |
| 247 | write32(mmiobase + PFIT_PGM_RATIOS, 0); |
| 248 | write32(mmiobase + PFIT_CONTROL, 0); |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 249 | } else { |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 250 | write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 251 | write32(mmiobase + PF_WIN_POS(0), 0); |
| 252 | write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); |
| 253 | write32(mmiobase + PFIT_CONTROL, PFIT_ENABLE |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 254 | | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE |
| 255 | | VERT_AUTO_SCALE); |
| 256 | } |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 257 | |
| 258 | mdelay(1); |
| 259 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 260 | write32(mmiobase + DSPCNTR(0), DISPPLANE_BGRX888 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 261 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 262 | |
| 263 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 264 | write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS |
| 265 | | (read32(mmiobase + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 266 | write32(mmiobase + FP0(1), |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 267 | (pixel_n << 16) |
| 268 | | (pixel_m1 << 8) | pixel_m2); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 269 | write32(mmiobase + DPLL(1), |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 270 | DPLL_VGA_MODE_DIS | |
| 271 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 272 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 273 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 274 | | (conf->gpu_lvds_use_spread_spectrum_clock |
| 275 | ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV |
| 276 | : 0) |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 277 | | (0x10000 << (pixel_p1 - 1))); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 278 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 279 | write32(mmiobase + DPLL(1), |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 280 | DPLL_VGA_MODE_DIS | |
| 281 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 282 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 283 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 284 | | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 285 | | (0x10000 << (pixel_p1 - 1))); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 286 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 287 | write32(mmiobase + HTOTAL(1), |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 288 | ((hactive + right_border + hblank - 1) << 16) |
| 289 | | (hactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 290 | write32(mmiobase + HBLANK(1), |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 291 | ((hactive + right_border + hblank - 1) << 16) |
| 292 | | (hactive + right_border - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 293 | write32(mmiobase + HSYNC(1), |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 294 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 295 | | (hactive + right_border + hfront_porch - 1)); |
| 296 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 297 | write32(mmiobase + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 298 | | (vactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 299 | write32(mmiobase + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 300 | | (vactive + bottom_border - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 301 | write32(mmiobase + VSYNC(1), |
Arthur Heymans | c8c73a6 | 2016-10-13 14:12:45 +0200 | [diff] [blame] | 302 | ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 303 | | (vactive + bottom_border + vfront_porch - 1)); |
| 304 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 305 | if (CONFIG(LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 306 | write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16) |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 307 | | (vactive - 1)); |
| 308 | } else { |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 309 | write32(mmiobase + PIPESRC(1), (639 << 16) | 399); |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 310 | } |
| 311 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 312 | mdelay(1); |
| 313 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 314 | write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); |
| 315 | write32(mmiobase + DSPPOS(0), 0); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 316 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 317 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 318 | write32(mmiobase + DSPADDR(0), 0); |
| 319 | write32(mmiobase + DSPSURF(0), 0); |
| 320 | write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line); |
| 321 | write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 322 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 323 | mdelay(1); |
| 324 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 325 | write32(mmiobase + PIPECONF(1), PIPECONF_ENABLE); |
| 326 | write32(mmiobase + LVDS, LVDS_ON |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 327 | | (hpolarity << 20) | (vpolarity << 21) |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 328 | | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 329 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 330 | | LVDS_CLOCK_A_POWERUP_ALL |
| 331 | | LVDS_PIPE(1)); |
| 332 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 333 | write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 334 | write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 335 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 336 | write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 337 | | PANEL_POWER_ON | PANEL_POWER_RESET); |
| 338 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 339 | printk(BIOS_DEBUG, "waiting for panel powerup\n"); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 340 | while (1) { |
| 341 | u32 reg32; |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 342 | reg32 = read32(mmiobase + PP_STATUS); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 343 | if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) |
| 344 | break; |
| 345 | } |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 346 | printk(BIOS_DEBUG, "panel powered up\n"); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 347 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 348 | write32(mmiobase + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 349 | |
| 350 | /* Clear interrupts. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 351 | write32(mmiobase + DEIIR, 0xffffffff); |
| 352 | write32(mmiobase + SDEIIR, 0xffffffff); |
| 353 | write32(mmiobase + IIR, 0xffffffff); |
| 354 | write32(mmiobase + IMR, 0xffffffff); |
| 355 | write32(mmiobase + EIR, 0xffffffff); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 356 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 357 | if (gtt_setup(mmiobase)) { |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 358 | printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | /* Setup GTT. */ |
| 363 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 364 | reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 365 | uma_size = 0; |
| 366 | if (!(reg16 & 2)) { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 367 | uma_size = decode_igd_memory_size((reg16 >> 4) & 7); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 368 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 369 | } |
| 370 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 371 | for (i = 0; i < (uma_size - 256) / 4; i++) { |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 372 | outl((i << 2) | 1, piobase); |
| 373 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 374 | } |
| 375 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 376 | temp = read32(mmiobase + PGETBL_CTL); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 377 | printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); |
| 378 | |
| 379 | if (temp & 1) |
| 380 | printk(BIOS_INFO, "GTT Enabled\n"); |
| 381 | else |
| 382 | printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); |
| 383 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 384 | if (CONFIG(LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 385 | printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", |
| 386 | (void *)pgfx, hactive * vactive * 4); |
| 387 | memset((void *)pgfx, 0x00, hactive * vactive * 4); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 388 | |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 389 | set_vbe_mode_info_valid(&edid, pgfx); |
| 390 | } else { |
| 391 | vga_misc_write(0x67); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 392 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 393 | write32(mmiobase + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); |
| 394 | write32(mmiobase + VGACNTRL, 0x02c4008e |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 395 | | VGA_PIPE_B_SELECT); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 396 | |
Arthur Heymans | 9c5fc62 | 2016-10-18 02:15:44 +0200 | [diff] [blame] | 397 | vga_textmode_init(); |
| 398 | } |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 399 | return 0; |
| 400 | } |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 401 | |
| 402 | static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, |
| 403 | unsigned int pphysbase, unsigned int piobase, |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 404 | u8 *mmiobase, unsigned int pgfx) |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 405 | { |
| 406 | int i; |
| 407 | u32 hactive, vactive; |
| 408 | u16 reg16; |
| 409 | u32 uma_size; |
| 410 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 411 | printk(BIOS_SPEW, "mmiobase %x addrport %x physbase %x\n", |
| 412 | (u32)mmiobase, piobase, pphysbase); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 413 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 414 | gtt_setup(mmiobase); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 415 | |
| 416 | /* Disable VGA. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 417 | write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 418 | |
| 419 | /* Disable pipes. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 420 | write32(mmiobase + PIPECONF(0), 0); |
| 421 | write32(mmiobase + PIPECONF(1), 0); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 422 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 423 | write32(mmiobase + INSTPM, 0x800); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 424 | |
| 425 | vga_gr_write(0x18, 0); |
| 426 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 427 | write32(mmiobase + VGA0, 0x200074); |
| 428 | write32(mmiobase + VGA1, 0x200074); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 429 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 430 | write32(mmiobase + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); |
| 431 | write32(mmiobase + DSPCLK_GATE_D, 0); |
| 432 | write32(mmiobase + FW_BLC, 0x03060106); |
| 433 | write32(mmiobase + FW_BLC2, 0x00000306); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 434 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 435 | write32(mmiobase + ADPA, ADPA_DAC_ENABLE |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 436 | | ADPA_PIPE_A_SELECT |
| 437 | | ADPA_USE_VGA_HVPOLARITY |
| 438 | | ADPA_VSYNC_CNTL_ENABLE |
| 439 | | ADPA_HSYNC_CNTL_ENABLE |
| 440 | | ADPA_DPMS_ON |
| 441 | ); |
| 442 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 443 | write32(mmiobase + 0x7041c, 0x0); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 444 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 445 | write32(mmiobase + DPLL_MD(0), 0x3); |
| 446 | write32(mmiobase + DPLL_MD(1), 0x3); |
| 447 | write32(mmiobase + DSPCNTR(1), 0x1000000); |
| 448 | write32(mmiobase + PIPESRC(1), 0x027f01df); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 449 | |
| 450 | vga_misc_write(0x67); |
| 451 | const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
| 452 | 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
| 453 | 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
| 454 | 0xff |
| 455 | }; |
| 456 | vga_cr_write(0x11, 0); |
| 457 | |
| 458 | for (i = 0; i <= 0x18; i++) |
| 459 | vga_cr_write(i, cr[i]); |
| 460 | |
| 461 | // Disable screen memory to prevent garbage from appearing. |
| 462 | vga_sr_write(1, vga_sr_read(1) | 0x20); |
| 463 | hactive = 640; |
| 464 | vactive = 400; |
| 465 | |
| 466 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 467 | write32(mmiobase + DPLL(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 468 | DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL |
| 469 | | DPLL_VGA_MODE_DIS |
| 470 | | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 |
| 471 | | 0x400601 |
| 472 | ); |
| 473 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 474 | write32(mmiobase + DPLL(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 475 | DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL |
| 476 | | DPLL_VGA_MODE_DIS |
| 477 | | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 |
| 478 | | 0x400601 |
| 479 | ); |
| 480 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 481 | write32(mmiobase + ADPA, ADPA_DAC_ENABLE |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 482 | | ADPA_PIPE_A_SELECT |
| 483 | | ADPA_USE_VGA_HVPOLARITY |
| 484 | | ADPA_VSYNC_CNTL_ENABLE |
| 485 | | ADPA_HSYNC_CNTL_ENABLE |
| 486 | | ADPA_DPMS_ON |
| 487 | ); |
| 488 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 489 | write32(mmiobase + HTOTAL(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 490 | ((hactive - 1) << 16) |
| 491 | | (hactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 492 | write32(mmiobase + HBLANK(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 493 | ((hactive - 1) << 16) |
| 494 | | (hactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 495 | write32(mmiobase + HSYNC(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 496 | ((hactive - 1) << 16) |
| 497 | | (hactive - 1)); |
| 498 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 499 | write32(mmiobase + VTOTAL(0), ((vactive - 1) << 16) |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 500 | | (vactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 501 | write32(mmiobase + VBLANK(0), ((vactive - 1) << 16) |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 502 | | (vactive - 1)); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 503 | write32(mmiobase + VSYNC(0), |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 504 | ((vactive - 1) << 16) |
| 505 | | (vactive - 1)); |
| 506 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 507 | write32(mmiobase + PF_WIN_POS(0), 0); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 508 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 509 | write32(mmiobase + PIPESRC(0), (639 << 16) | 399); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 510 | write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 511 | write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 512 | write32(mmiobase + PFIT_CONTROL, 0x0); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 513 | |
| 514 | mdelay(1); |
| 515 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 516 | write32(mmiobase + FDI_RX_CTL(0), 0x00002040); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 517 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 518 | write32(mmiobase + FDI_RX_CTL(0), 0x80002050); |
| 519 | write32(mmiobase + FDI_TX_CTL(0), 0x00044000); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 520 | mdelay(1); |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 521 | write32(mmiobase + FDI_TX_CTL(0), 0x80044000); |
| 522 | write32(mmiobase + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 523 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 524 | write32(mmiobase + VGACNTRL, 0x0); |
| 525 | write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 526 | mdelay(1); |
| 527 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 528 | write32(mmiobase + ADPA, ADPA_DAC_ENABLE |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 529 | | ADPA_PIPE_A_SELECT |
| 530 | | ADPA_USE_VGA_HVPOLARITY |
| 531 | | ADPA_VSYNC_CNTL_ENABLE |
| 532 | | ADPA_HSYNC_CNTL_ENABLE |
| 533 | | ADPA_DPMS_ON |
| 534 | ); |
| 535 | |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 536 | write32(mmiobase + DSPFW3, 0x7f3f00c1); |
| 537 | write32(mmiobase + MI_MODE, 0x200 | VS_TIMER_DISPATCH); |
| 538 | write32(mmiobase + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); |
| 539 | write32(mmiobase + CACHE_MODE_1, 0x380 & ~(1 << 9)); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 540 | |
| 541 | /* Set up GTT. */ |
| 542 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 543 | reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 544 | uma_size = 0; |
| 545 | if (!(reg16 & 2)) { |
| 546 | uma_size = decode_igd_memory_size((reg16 >> 4) & 7); |
| 547 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 548 | } |
| 549 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 550 | for (i = 0; i < (uma_size - 256) / 4; i++) { |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 551 | outl((i << 2) | 1, piobase); |
| 552 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 553 | } |
| 554 | |
| 555 | /* Clear interrupts. */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 556 | write32(mmiobase + DEIIR, 0xffffffff); |
| 557 | write32(mmiobase + SDEIIR, 0xffffffff); |
| 558 | write32(mmiobase + IIR, 0xffffffff); |
| 559 | write32(mmiobase + IMR, 0xffffffff); |
| 560 | write32(mmiobase + EIR, 0xffffffff); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 561 | |
| 562 | vga_textmode_init(); |
| 563 | |
| 564 | /* Enable screen memory. */ |
| 565 | vga_sr_write(1, vga_sr_read(1) & ~0x20); |
| 566 | |
| 567 | return 0; |
| 568 | |
| 569 | } |
| 570 | |
| 571 | /* compare the header of the vga edid header */ |
| 572 | /* if vga is not connected it should have a correct header */ |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 573 | static int probe_edid(u8 *mmiobase, u8 slave) |
Arthur Heymans | 62f4dad | 2016-09-06 23:53:32 +0200 | [diff] [blame] | 574 | { |
Paul Menzel | 533a385 | 2016-11-27 22:17:44 +0100 | [diff] [blame] | 575 | int i; |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 576 | u8 vga_edid[128]; |
| 577 | u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; |
Arthur Heymans | 85cfddb | 2017-02-06 13:47:21 +0100 | [diff] [blame] | 578 | intel_gmbus_read_edid(mmiobase + GMBUS0, slave, 0x50, vga_edid, 128); |
| 579 | intel_gmbus_stop(mmiobase + GMBUS0); |
Paul Menzel | 533a385 | 2016-11-27 22:17:44 +0100 | [diff] [blame] | 580 | for (i = 0; i < 8; i++) { |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 581 | if (vga_edid[i] != header[i]) { |
Arthur Heymans | 62f4dad | 2016-09-06 23:53:32 +0200 | [diff] [blame] | 582 | printk(BIOS_DEBUG, "No display connected on slave %d\n", |
| 583 | slave); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 584 | return 0; |
| 585 | } |
| 586 | } |
Arthur Heymans | 62f4dad | 2016-09-06 23:53:32 +0200 | [diff] [blame] | 587 | printk(BIOS_SPEW, "Found a display on slave %d\n", slave); |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 588 | return 1; |
| 589 | } |
| 590 | |
Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 591 | static u32 get_cdclk(struct device *const dev) |
| 592 | { |
| 593 | u16 gcfgc = pci_read_config16(dev, GCFGC); |
| 594 | |
Elyes HAOUAS | 2a1c430 | 2018-10-25 10:41:27 +0200 | [diff] [blame] | 595 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 596 | return 133333333; |
Elyes HAOUAS | 2a1c430 | 2018-10-25 10:41:27 +0200 | [diff] [blame] | 597 | |
| 598 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 599 | case GC_DISPLAY_CLOCK_333_320_MHZ: |
| 600 | return 320000000; |
| 601 | default: |
| 602 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 603 | return 200000000; |
Arthur Heymans | 8e07900 | 2017-01-14 22:31:54 +0100 | [diff] [blame] | 604 | } |
| 605 | } |
| 606 | |
| 607 | static u32 freq_to_blc_pwm_ctl(struct device *const dev, u16 pwm_freq) |
| 608 | { |
| 609 | u32 blc_mod; |
| 610 | |
| 611 | /* Set duty cycle to 100% due to use of legacy backlight control */ |
| 612 | blc_mod = get_cdclk(dev) / (32 * pwm_freq); |
| 613 | return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); |
| 614 | } |
| 615 | |
| 616 | |
| 617 | static void panel_setup(u8 *mmiobase, struct device *const dev) |
| 618 | { |
| 619 | const struct northbridge_intel_i945_config *const conf = dev->chip_info; |
| 620 | |
| 621 | u32 reg32; |
| 622 | |
| 623 | /* Set up Panel Power On Delays */ |
| 624 | reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 625 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 626 | write32(mmiobase + PP_ON_DELAYS, reg32); |
| 627 | |
| 628 | /* Set up Panel Power Off Delays */ |
| 629 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 630 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 631 | write32(mmiobase + PP_OFF_DELAYS, reg32); |
| 632 | |
| 633 | /* Set up Panel Power Cycle Delay */ |
| 634 | reg32 = (get_cdclk(dev) / 20000 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 635 | reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; |
| 636 | write32(mmiobase + PP_DIVISOR, reg32); |
| 637 | |
| 638 | /* Backlight init. */ |
| 639 | if (conf->pwm_freq) |
| 640 | write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, |
| 641 | conf->pwm_freq)); |
| 642 | else |
| 643 | write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, |
| 644 | DEFAULT_BLC_PWM)); |
| 645 | } |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 646 | |
Paul Menzel | b23833f | 2018-04-26 19:53:31 +0200 | [diff] [blame] | 647 | static void gma_ngi(struct device *const dev) |
| 648 | { |
| 649 | /* This should probably run before post VBIOS init. */ |
| 650 | printk(BIOS_INFO, "Initializing VGA without OPROM.\n"); |
| 651 | void *mmiobase; |
| 652 | u32 iobase, graphics_base; |
| 653 | struct northbridge_intel_i945_config *conf = dev->chip_info; |
| 654 | |
| 655 | iobase = dev->resource_list[1].base; |
| 656 | mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; |
| 657 | graphics_base = dev->resource_list[2].base; |
| 658 | |
| 659 | printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n", |
| 660 | pci_read_config32(dev, GMADR), pci_read_config32(dev, GTTADR)); |
| 661 | |
| 662 | int err; |
| 663 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 664 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Paul Menzel | b23833f | 2018-04-26 19:53:31 +0200 | [diff] [blame] | 665 | panel_setup(mmiobase, dev); |
| 666 | |
| 667 | /* probe if VGA is connected and always run */ |
| 668 | /* VGA init if no LVDS is connected */ |
| 669 | if (!probe_edid(mmiobase, GMBUS_PORT_PANEL) || |
| 670 | probe_edid(mmiobase, GMBUS_PORT_VGADDC)) |
| 671 | err = intel_gma_init_vga(conf, |
| 672 | pci_read_config32(dev, 0x5c) & ~0xf, |
| 673 | iobase, mmiobase, graphics_base); |
| 674 | else |
| 675 | err = intel_gma_init_lvds(conf, |
| 676 | pci_read_config32(dev, 0x5c) & ~0xf, |
| 677 | iobase, mmiobase, graphics_base); |
| 678 | if (err == 0) |
| 679 | gfx_set_init_done(1); |
| 680 | /* Linux relies on VBT for panel info. */ |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 681 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Paul Menzel | b23833f | 2018-04-26 19:53:31 +0200 | [diff] [blame] | 682 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA"); |
| 683 | } |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 684 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Paul Menzel | b23833f | 2018-04-26 19:53:31 +0200 | [diff] [blame] | 685 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G"); |
| 686 | } |
| 687 | } |
| 688 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 689 | static void gma_func0_init(struct device *dev) |
| 690 | { |
| 691 | u32 reg32; |
| 692 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 693 | /* Unconditionally reset graphics */ |
| 694 | pci_write_config8(dev, GDRST, 1); |
| 695 | udelay(50); |
| 696 | pci_write_config8(dev, GDRST, 0); |
| 697 | /* wait for device to finish */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 698 | while (pci_read_config8(dev, GDRST) & 1) |
| 699 | ; |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 700 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 701 | /* IGD needs to be Bus Master */ |
| 702 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 703 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER |
| 704 | | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 705 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 706 | if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { |
Elyes HAOUAS | 8881d57 | 2019-07-14 09:16:58 +0200 | [diff] [blame] | 707 | int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 708 | if (acpi_is_wakeup_s3()) { |
Paul Menzel | 5e7ad65 | 2018-04-14 20:08:54 +0200 | [diff] [blame] | 709 | printk(BIOS_INFO, |
| 710 | "Skipping native VGA initialization when resuming from ACPI S3.\n"); |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 711 | } else { |
| 712 | if (vga_disable) { |
| 713 | printk(BIOS_INFO, |
| 714 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
| 715 | } else { |
| 716 | gma_ngi(dev); |
| 717 | } |
| 718 | } |
Arthur Heymans | f3f4bea | 2016-10-20 20:44:54 +0200 | [diff] [blame] | 719 | } else { |
| 720 | /* PCI Init, will run VBIOS */ |
| 721 | pci_dev_init(dev); |
Arthur Heymans | 333176e | 2016-09-07 22:10:57 +0200 | [diff] [blame] | 722 | } |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 723 | |
| 724 | intel_gma_restore_opregion(); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 725 | } |
| 726 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 727 | /* This doesn't reclaim stolen UMA memory, but IGD could still |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 728 | be re-enabled later. */ |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 729 | static void gma_func0_disable(struct device *dev) |
| 730 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 731 | struct device *dev_host = pcidev_on_root(0x0, 0); |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 732 | |
| 733 | pci_write_config16(dev, GCFC, 0xa00); |
| 734 | pci_write_config16(dev_host, GGC, (1 << 1)); |
| 735 | |
| 736 | unsigned int reg32 = pci_read_config32(dev_host, DEVEN); |
| 737 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 738 | pci_write_config32(dev_host, DEVEN, reg32); |
| 739 | |
| 740 | dev->enabled = 0; |
| 741 | } |
| 742 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 743 | static void gma_func1_init(struct device *dev) |
| 744 | { |
| 745 | u32 reg32; |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 746 | u8 val; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 747 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 748 | /* IGD needs to be Bus Master, also enable IO access */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 749 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 750 | pci_write_config32(dev, PCI_COMMAND, reg32 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 751 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 752 | |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 753 | if (get_option(&val, "tft_brightness") == CB_SUCCESS) |
| 754 | pci_write_config8(dev, 0xf4, val); |
| 755 | else |
| 756 | pci_write_config8(dev, 0xf4, 0xff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 757 | } |
| 758 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 759 | const struct i915_gpu_controller_info * |
| 760 | intel_gma_get_controller_info(void) |
| 761 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 762 | struct device *dev = pcidev_on_root(0x2, 0); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 763 | if (!dev) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 764 | return NULL; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 765 | struct northbridge_intel_i945_config *chip = dev->chip_info; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 766 | if (!chip) |
Patrick Georgi | 54e227e | 2015-08-08 22:02:12 +0200 | [diff] [blame] | 767 | return NULL; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 768 | return &chip->gfx; |
| 769 | } |
| 770 | |
Elyes HAOUAS | 658a934 | 2018-02-08 14:46:22 +0100 | [diff] [blame] | 771 | static void gma_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 772 | { |
| 773 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 774 | if (!gfx) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 775 | return; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 776 | |
| 777 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 778 | } |
| 779 | |
Elyes HAOUAS | 658a934 | 2018-02-08 14:46:22 +0100 | [diff] [blame] | 780 | static void gma_func0_read_resources(struct device *dev) |
Arthur Heymans | c057a061 | 2016-10-22 14:16:48 +0200 | [diff] [blame] | 781 | { |
| 782 | u8 reg8; |
| 783 | |
| 784 | /* Set Untrusted Aperture Size to 256mb */ |
| 785 | reg8 = pci_read_config8(dev, MSAC); |
| 786 | reg8 &= ~0x3; |
| 787 | reg8 |= 0x2; |
| 788 | pci_write_config8(dev, MSAC, reg8); |
| 789 | |
| 790 | pci_dev_read_resources(dev); |
| 791 | } |
| 792 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 793 | static unsigned long |
| 794 | gma_write_acpi_tables(struct device *const dev, |
| 795 | unsigned long current, |
| 796 | struct acpi_rsdp *const rsdp) |
| 797 | { |
| 798 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 799 | global_nvs_t *gnvs; |
| 800 | |
| 801 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 802 | return current; |
| 803 | |
| 804 | current += sizeof(igd_opregion_t); |
| 805 | |
| 806 | /* GNVS has been already set up */ |
| 807 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 808 | if (gnvs) { |
| 809 | /* IGD OpRegion Base Address */ |
| 810 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 811 | } else { |
| 812 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 813 | } |
| 814 | |
| 815 | current = acpi_align_current(current); |
| 816 | return current; |
| 817 | } |
| 818 | |
| 819 | static const char *gma_acpi_name(const struct device *dev) |
| 820 | { |
| 821 | return "GFX0"; |
| 822 | } |
| 823 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 824 | static struct pci_operations gma_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 825 | .set_subsystem = pci_dev_set_subsystem, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 826 | }; |
| 827 | |
| 828 | static struct device_operations gma_func0_ops = { |
Arthur Heymans | c057a061 | 2016-10-22 14:16:48 +0200 | [diff] [blame] | 829 | .read_resources = gma_func0_read_resources, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 830 | .set_resources = pci_dev_set_resources, |
| 831 | .enable_resources = pci_dev_enable_resources, |
| 832 | .init = gma_func0_init, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 833 | .acpi_fill_ssdt_generator = gma_ssdt, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 834 | .scan_bus = 0, |
| 835 | .enable = 0, |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 836 | .disable = gma_func0_disable, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 837 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 838 | .acpi_name = gma_acpi_name, |
| 839 | .write_acpi_tables = gma_write_acpi_tables, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 840 | }; |
| 841 | |
| 842 | |
| 843 | static struct device_operations gma_func1_ops = { |
| 844 | .read_resources = pci_dev_read_resources, |
| 845 | .set_resources = pci_dev_set_resources, |
| 846 | .enable_resources = pci_dev_enable_resources, |
| 847 | .init = gma_func1_init, |
| 848 | .scan_bus = 0, |
| 849 | .enable = 0, |
| 850 | .ops_pci = &gma_pci_ops, |
| 851 | }; |
| 852 | |
Elyes HAOUAS | a299345 | 2016-10-28 10:56:59 +0200 | [diff] [blame] | 853 | static const unsigned short i945_gma_func0_ids[] = { |
| 854 | 0x2772, /* 82945G/GZ Integrated Graphics Controller */ |
| 855 | 0x27a2, /* Mobile 945GM/GMS Express Integrated Graphics Controller*/ |
| 856 | 0x27ae, /* Mobile 945GSE Express Integrated Graphics Controller */ |
| 857 | 0 |
| 858 | }; |
| 859 | |
| 860 | static const unsigned short i945_gma_func1_ids[] = { |
Elyes HAOUAS | 686b539 | 2019-05-18 13:36:03 +0200 | [diff] [blame] | 861 | 0x2776, /* Desktop 82945G/GZ/GC */ |
Elyes HAOUAS | a299345 | 2016-10-28 10:56:59 +0200 | [diff] [blame] | 862 | 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ |
| 863 | 0 |
| 864 | }; |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 865 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 866 | static const struct pci_driver i945_gma_func0_driver __pci_driver = { |
Paul Menzel | 82683c0 | 2018-04-14 19:56:46 +0200 | [diff] [blame] | 867 | .ops = &gma_func0_ops, |
| 868 | .vendor = PCI_VENDOR_ID_INTEL, |
Elyes HAOUAS | a299345 | 2016-10-28 10:56:59 +0200 | [diff] [blame] | 869 | .devices = i945_gma_func0_ids, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 870 | }; |
| 871 | |
| 872 | static const struct pci_driver i945_gma_func1_driver __pci_driver = { |
Paul Menzel | 82683c0 | 2018-04-14 19:56:46 +0200 | [diff] [blame] | 873 | .ops = &gma_func1_ops, |
| 874 | .vendor = PCI_VENDOR_ID_INTEL, |
Elyes HAOUAS | a299345 | 2016-10-28 10:56:59 +0200 | [diff] [blame] | 875 | .devices = i945_gma_func1_ids, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 876 | }; |