blob: 20e8bf3667d1c86305154380e395f43bd0bfdfd2 [file] [log] [blame]
Stefan Reinauer30140a52009-03-11 16:20:39 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer30140a52009-03-11 16:20:39 +000018 */
19
20#include <console/console.h>
Patrick Georgi6444bd42012-07-06 11:31:39 +020021#include <delay.h>
Stefan Reinauer30140a52009-03-11 16:20:39 +000022#include <device/device.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
Sven Schnelleb629d142011-06-12 14:30:10 +020025#include <pc80/mc146818rtc.h>
Patrick Georgice6e9fe2012-07-20 12:37:06 +020026#include "i945.h"
Stefan Reinauer30140a52009-03-11 16:20:39 +000027
Patrick Georgi6444bd42012-07-06 11:31:39 +020028#define GDRST 0xc0
29
Stefan Reinauer30140a52009-03-11 16:20:39 +000030static void gma_func0_init(struct device *dev)
31{
32 u32 reg32;
33
Patrick Georgi6444bd42012-07-06 11:31:39 +020034 /* Unconditionally reset graphics */
35 pci_write_config8(dev, GDRST, 1);
36 udelay(50);
37 pci_write_config8(dev, GDRST, 0);
38 /* wait for device to finish */
39 while (pci_read_config8(dev, GDRST) & 1) { };
40
Stefan Reinauer30140a52009-03-11 16:20:39 +000041 /* IGD needs to be Bus Master */
42 reg32 = pci_read_config32(dev, PCI_COMMAND);
43 pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
44
Denis 'GNUtoo' Cariklied7e29e2013-02-24 12:01:44 +010045
46#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
47 /* PCI Init, will run VBIOS */
Stefan Reinauer30140a52009-03-11 16:20:39 +000048 pci_dev_init(dev);
Denis 'GNUtoo' Cariklied7e29e2013-02-24 12:01:44 +010049#endif
50
51
52#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
53 /* This should probably run before post VBIOS init. */
54 printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
55 u32 iobase, mmiobase, physbase, graphics_base;
56 iobase = dev->resource_list[1].base;
57 mmiobase = dev->resource_list[0].base;
58 physbase = pci_read_config32(dev, 0x5c) & ~0xf;
59 graphics_base = dev->resource_list[2].base + 0x20000 ;
60
61 int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
62 i915lightup(physbase, iobase, mmiobase, graphics_base);
63#endif
64
Stefan Reinauer30140a52009-03-11 16:20:39 +000065}
66
Patrick Georgice6e9fe2012-07-20 12:37:06 +020067/* This doesn't reclaim stolen UMA memory, but IGD could still
68 be reenabled later. */
69static void gma_func0_disable(struct device *dev)
70{
71 struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
72
73 pci_write_config16(dev, GCFC, 0xa00);
74 pci_write_config16(dev_host, GGC, (1 << 1));
75
76 unsigned int reg32 = pci_read_config32(dev_host, DEVEN);
77 reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
78 pci_write_config32(dev_host, DEVEN, reg32);
79
80 dev->enabled = 0;
81}
82
Stefan Reinauer30140a52009-03-11 16:20:39 +000083static void gma_func1_init(struct device *dev)
84{
85 u32 reg32;
Sven Schnelleb629d142011-06-12 14:30:10 +020086 u8 val;
Stefan Reinauer30140a52009-03-11 16:20:39 +000087
88 /* IGD needs to be Bus Master, also enable IO accesss */
89 reg32 = pci_read_config32(dev, PCI_COMMAND);
Stefan Reinauer109ab312009-08-12 16:08:05 +000090 pci_write_config32(dev, PCI_COMMAND, reg32 |
Stefan Reinauer30140a52009-03-11 16:20:39 +000091 PCI_COMMAND_MASTER | PCI_COMMAND_IO);
Sven Schnelleb629d142011-06-12 14:30:10 +020092
93 if (!get_option(&val, "tft_brightness"))
94 pci_write_config8(dev, 0xf4, val);
95 else
96 pci_write_config8(dev, 0xf4, 0xff);
Stefan Reinauer30140a52009-03-11 16:20:39 +000097}
98
99static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
100{
101 if (!vendor || !device) {
102 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
103 pci_read_config32(dev, PCI_VENDOR_ID));
104 } else {
105 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
106 ((device & 0xffff) << 16) | (vendor & 0xffff));
107 }
108}
109
110static struct pci_operations gma_pci_ops = {
111 .set_subsystem = gma_set_subsystem,
112};
113
114static struct device_operations gma_func0_ops = {
115 .read_resources = pci_dev_read_resources,
116 .set_resources = pci_dev_set_resources,
117 .enable_resources = pci_dev_enable_resources,
118 .init = gma_func0_init,
119 .scan_bus = 0,
120 .enable = 0,
Patrick Georgice6e9fe2012-07-20 12:37:06 +0200121 .disable = gma_func0_disable,
Stefan Reinauer30140a52009-03-11 16:20:39 +0000122 .ops_pci = &gma_pci_ops,
123};
124
125
126static struct device_operations gma_func1_ops = {
127 .read_resources = pci_dev_read_resources,
128 .set_resources = pci_dev_set_resources,
129 .enable_resources = pci_dev_enable_resources,
130 .init = gma_func1_init,
131 .scan_bus = 0,
132 .enable = 0,
133 .ops_pci = &gma_pci_ops,
134};
135
136static const struct pci_driver i945_gma_func0_driver __pci_driver = {
137 .ops = &gma_func0_ops,
138 .vendor = PCI_VENDOR_ID_INTEL,
139 .device = 0x27a2,
140};
141
142static const struct pci_driver i945_gma_func1_driver __pci_driver = {
143 .ops = &gma_func1_ops,
144 .vendor = PCI_VENDOR_ID_INTEL,
145 .device = 0x27a6,
146};
147