Martin Roth | 1908110 | 2024-02-16 10:31:30 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Arthur Heymans | 67f29e8 | 2022-04-17 10:37:13 +0200 | [diff] [blame] | 3 | if ARCH_X86 |
| 4 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 5 | config PARALLEL_MP |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 6 | def_bool y |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 7 | help |
| 8 | This option uses common MP infrastructure for bringing up APs |
| 9 | in parallel. It additionally provides a more flexible mechanism |
| 10 | for sequencing the steps of bringing up the APs. |
Arthur Heymans | 48fbf2f | 2021-11-26 14:50:42 +0100 | [diff] [blame] | 11 | The code also works for just initialising the BSP in case there |
| 12 | are no APs. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 13 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 14 | config PARALLEL_MP_AP_WORK |
| 15 | def_bool n |
| 16 | depends on PARALLEL_MP |
| 17 | help |
| 18 | Allow APs to do other work after initialization instead of going |
| 19 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 20 | |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 21 | config X86_SMM_SKIP_RELOCATION_HANDLER |
| 22 | bool |
| 23 | default n |
| 24 | depends on PARALLEL_MP && HAVE_SMI_HANDLER |
| 25 | help |
| 26 | Skip SMM relocation using a relocation handler running in SMM |
| 27 | with a stub at 0x30000. This is useful on platforms that have |
| 28 | an alternative way to set SMBASE. |
| 29 | |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 30 | config DEFAULT_X2APIC |
| 31 | def_bool n |
| 32 | help |
Martin Roth | 53b1929 | 2023-05-10 13:28:42 -0600 | [diff] [blame] | 33 | Allow SoC code to set LAPIC access mode to X2APIC. |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 34 | |
| 35 | config DEFAULT_X2APIC_RUNTIME |
| 36 | def_bool n |
| 37 | help |
Martin Roth | 53b1929 | 2023-05-10 13:28:42 -0600 | [diff] [blame] | 38 | Allow SoC code to set LAPIC access mode to X2APIC_RUNTIME. |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 39 | |
Subrata Banik | 55d300c | 2022-07-12 11:06:15 +0000 | [diff] [blame] | 40 | config DEFAULT_X2APIC_LATE_WORKAROUND |
| 41 | def_bool n |
| 42 | help |
Martin Roth | 53b1929 | 2023-05-10 13:28:42 -0600 | [diff] [blame] | 43 | Allow SoC code to set LAPIC access mode to X2APIC_LATE_WORKAROUND. |
Subrata Banik | 55d300c | 2022-07-12 11:06:15 +0000 | [diff] [blame] | 44 | |
Martin Roth | 53b1929 | 2023-05-10 13:28:42 -0600 | [diff] [blame] | 45 | choice |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 46 | prompt "APIC operation mode" |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 47 | default X2APIC_ONLY if DEFAULT_X2APIC |
| 48 | default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME |
Subrata Banik | 55d300c | 2022-07-12 11:06:15 +0000 | [diff] [blame] | 49 | default X2APIC_LATE_WORKAROUND if DEFAULT_X2APIC_LATE_WORKAROUND |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 50 | default XAPIC_ONLY |
| 51 | |
| 52 | config XAPIC_ONLY |
| 53 | prompt "Set XAPIC mode" |
| 54 | bool |
Kyösti Mälkki | a52b93b | 2023-06-30 18:44:26 +0300 | [diff] [blame] | 55 | help |
| 56 | coreboot and SMM runtime only use XAPIC mode. |
| 57 | FIXME: DMAR should have X2APIC optout bit set. |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 58 | |
| 59 | config X2APIC_ONLY |
| 60 | prompt "Set X2APIC mode" |
| 61 | bool |
| 62 | depends on PARALLEL_MP |
Kyösti Mälkki | a52b93b | 2023-06-30 18:44:26 +0300 | [diff] [blame] | 63 | help |
| 64 | coreboot and SMM runtime only use X2APIC mode. |
| 65 | Note: OS switches back to XAPIC mode if VT-d is disabled. |
| 66 | FIXME: S3 resume (and SMM runtime) will break if OS makes the switch. |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 67 | |
| 68 | config X2APIC_RUNTIME |
| 69 | prompt "Support both XAPIC and X2APIC" |
| 70 | bool |
| 71 | depends on PARALLEL_MP |
Kyösti Mälkki | a52b93b | 2023-06-30 18:44:26 +0300 | [diff] [blame] | 72 | help |
| 73 | The switch to X2APIC mode happens early in ramstage. SMM runtime can |
| 74 | support either mode in case the OS switches back to XAPIC. |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 75 | |
Subrata Banik | 2125a17 | 2022-07-12 10:55:21 +0000 | [diff] [blame] | 76 | config X2APIC_LATE_WORKAROUND |
| 77 | prompt "Use XAPIC for AP bringup, then change to X2APIC" |
| 78 | bool |
Subrata Banik | fb28799 | 2022-07-24 11:19:04 +0530 | [diff] [blame] | 79 | depends on PARALLEL_MP && MAX_CPUS < 256 |
Subrata Banik | 2125a17 | 2022-07-12 10:55:21 +0000 | [diff] [blame] | 80 | help |
| 81 | Choose this option if the platform supports dynamic switching between |
| 82 | XAPIC to X2APIC. The initial Application Processors (APs) are configured |
| 83 | in XAPIC mode at reset and later enable X2APIC as a CPU feature. |
| 84 | All access mechanisms between XAPIC (mmio) and X2APIC (msr) switches |
| 85 | at runtime when this option is enabled. |
| 86 | |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 87 | endchoice |
| 88 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 89 | config UDELAY_LAPIC |
| 90 | bool |
| 91 | default n |
| 92 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 93 | config LAPIC_MONOTONIC_TIMER |
| 94 | def_bool n |
| 95 | depends on UDELAY_LAPIC |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 96 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 97 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 98 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 99 | config UDELAY_LAPIC_FIXED_FSB |
| 100 | int |
| 101 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 102 | config UDELAY_TSC |
| 103 | bool |
| 104 | default n |
| 105 | |
Kyösti Mälkki | 0d6ddf8 | 2019-10-31 14:52:20 +0200 | [diff] [blame] | 106 | config UNKNOWN_TSC_RATE |
| 107 | bool |
| 108 | default y if LAPIC_MONOTONIC_TIMER |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 109 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 110 | config TSC_MONOTONIC_TIMER |
| 111 | def_bool n |
| 112 | depends on UDELAY_TSC |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 113 | help |
| 114 | Expose monotonic time using the TSC. |
| 115 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 116 | config TSC_SYNC_LFENCE |
| 117 | bool |
| 118 | default n |
| 119 | help |
| 120 | The CPU driver should select this if the CPU needs |
| 121 | to execute an lfence instruction in order to synchronize |
| 122 | rdtsc. This is true for all modern AMD CPUs. |
| 123 | |
| 124 | config TSC_SYNC_MFENCE |
| 125 | bool |
| 126 | default n |
| 127 | help |
| 128 | The CPU driver should select this if the CPU needs |
| 129 | to execute an mfence instruction in order to synchronize |
| 130 | rdtsc. This is true for all modern Intel CPUs. |
| 131 | |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 132 | config SETUP_XIP_CACHE |
| 133 | bool |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 134 | depends on !NO_XIP_EARLY_STAGES |
| 135 | help |
| 136 | Select this option to set up an MTRR to cache XIP stages loaded |
| 137 | from the bootblock. This is useful on platforms lacking a |
| 138 | non-eviction mode and therefore need to be careful to avoid |
| 139 | eviction. |
| 140 | |
Arthur Heymans | 3134a81 | 2019-11-25 12:20:01 +0100 | [diff] [blame] | 141 | config X86_CLFLUSH_CAR |
| 142 | bool |
| 143 | help |
| 144 | Select this on platforms that allow CLFLUSH while operating in CAR. |
| 145 | |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 146 | config HAVE_SMI_HANDLER |
| 147 | bool |
| 148 | default n |
| 149 | depends on (SMM_ASEG || SMM_TSEG) |
| 150 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 151 | config NO_SMM |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 152 | bool |
| 153 | default n |
| 154 | |
Ashish Kumar Mishra | ecbc243 | 2024-01-16 16:23:03 +0530 | [diff] [blame] | 155 | config USE_1G_PAGES_TLB |
| 156 | bool |
| 157 | default n |
| 158 | help |
| 159 | Select this option to enable access to up to 512 GiB of memory |
| 160 | by using 1 GiB large pages. |
| 161 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 162 | config SMM_ASEG |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 163 | bool |
| 164 | default n |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 165 | depends on !NO_SMM |
| 166 | |
| 167 | config SMM_TSEG |
| 168 | bool |
| 169 | default y |
| 170 | depends on !(NO_SMM || SMM_ASEG) |
| 171 | |
Arthur Heymans | 66b2888 | 2022-11-01 23:45:59 +0100 | [diff] [blame] | 172 | if HAVE_SMI_HANDLER |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 173 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 174 | config SMM_MODULE_STACK_SIZE |
| 175 | hex |
Patrick Rudolph | ed8d777 | 2021-06-12 06:21:27 +0200 | [diff] [blame] | 176 | default 0x800 if ARCH_RAMSTAGE_X86_64 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 177 | default 0x400 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 178 | help |
| 179 | This option determines the size of the stack within the SMM handler |
| 180 | modules. |
| 181 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 182 | endif |
| 183 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 184 | config SMM_LAPIC_REMAP_MITIGATION |
| 185 | bool |
Arthur Heymans | 912a262 | 2019-11-28 09:48:26 +0100 | [diff] [blame] | 186 | default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ |
| 187 | || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 188 | || NORTHBRIDGE_INTEL_E7505 || NORTHBRIDGE_INTEL_IRONLAKE |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 189 | default n |
| 190 | |
Robert Zieba | ac8c378 | 2022-09-07 16:25:15 -0600 | [diff] [blame] | 191 | config SMM_PCI_RESOURCE_STORE |
| 192 | bool |
| 193 | default n |
| 194 | help |
| 195 | This option enables support for storing PCI resources in SMRAM so |
| 196 | SMM can tell if they've been altered. |
| 197 | |
| 198 | config SMM_PCI_RESOURCE_STORE_NUM_SLOTS |
| 199 | int |
| 200 | default 8 |
| 201 | help |
| 202 | Number of slots available to store PCI BARs in SMRAM |
| 203 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 204 | config X86_AMD_FIXED_MTRRS |
| 205 | bool |
| 206 | default n |
| 207 | help |
| 208 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 209 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 210 | |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 211 | config X86_INIT_NEED_1_SIPI |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 212 | bool |
| 213 | default n |
| 214 | help |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 215 | This option limits the number of SIPI signals sent during the |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 216 | common AP setup. Intel documentation specifies an INIT SIPI SIPI |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 217 | sequence, however this doesn't work on some AMD and Intel platforms. |
| 218 | These newer AMD and Intel platforms don't need the 10ms wait between |
| 219 | INIT and SIPI, so skip that too to save some time. |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 220 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 221 | config SOC_SETS_MSRS |
| 222 | bool |
| 223 | default n |
| 224 | help |
| 225 | The SoC requires different access methods for reading and writing |
| 226 | the MSRs. Use SoC specific routines to handle the MSR access. |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 227 | |
| 228 | config RESERVE_MTRRS_FOR_OS |
| 229 | bool |
| 230 | default n |
| 231 | help |
| 232 | This option allows a platform to reserve 2 MTRRs for the OS usage. |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 233 | The Intel SDM documents that the first 6 MTRRs are intended for |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 234 | the system BIOS and the last 2 are to be reserved for OS usage. |
| 235 | However, modern OSes use PAT to control cacheability instead of |
| 236 | using MTRRs. |
Raul E Rangel | b2346a5 | 2021-09-22 14:56:51 -0600 | [diff] [blame] | 237 | |
Arthur Heymans | 4d75dbd | 2022-11-01 23:57:24 +0100 | [diff] [blame] | 238 | config AP_STACK_SIZE |
| 239 | hex |
| 240 | default 0x800 |
| 241 | help |
| 242 | This is the amount of stack each AP needs. The BSP stack size can be |
| 243 | larger and is set with STACK_SIZE. |
| 244 | |
Johnny Lin | 107e7aa | 2021-01-14 17:49:08 +0800 | [diff] [blame] | 245 | config RUNTIME_CONFIGURABLE_SMM_LOGLEVEL |
| 246 | bool |
| 247 | default n |
| 248 | depends on DEBUG_SMI && CONSOLE_OVERRIDE_LOGLEVEL |
| 249 | help |
| 250 | This enables setting the SMM console log level at runtime for more |
| 251 | flexibility to use different log levels for each stage. Another reason |
| 252 | is that reading the log level from non-volatile memory such as flash |
| 253 | VPD or CMOS is not very ideal to be done in SMM, with this option the |
| 254 | value can be passed via the member variable in struct smm_runtime and |
| 255 | be referenced directly in SMM. |
| 256 | |
Arthur Heymans | 67f29e8 | 2022-04-17 10:37:13 +0200 | [diff] [blame] | 257 | endif # ARCH_X86 |