Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 1 | config PARALLEL_MP |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 2 | def_bool y |
| 3 | depends on !LEGACY_SMP_INIT |
Raul E Rangel | 99c8478 | 2021-10-08 13:10:38 -0600 | [diff] [blame] | 4 | select CPU_INFO_V2 |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 5 | help |
| 6 | This option uses common MP infrastructure for bringing up APs |
| 7 | in parallel. It additionally provides a more flexible mechanism |
| 8 | for sequencing the steps of bringing up the APs. |
Arthur Heymans | 48fbf2f | 2021-11-26 14:50:42 +0100 | [diff] [blame^] | 9 | The code also works for just initialising the BSP in case there |
| 10 | are no APs. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 11 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 12 | config PARALLEL_MP_AP_WORK |
| 13 | def_bool n |
| 14 | depends on PARALLEL_MP |
| 15 | help |
| 16 | Allow APs to do other work after initialization instead of going |
| 17 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 18 | |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 19 | config LEGACY_SMP_INIT |
| 20 | bool |
| 21 | |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 22 | choice LAPIC_ACCESS_MODE |
| 23 | prompt "APIC operation mode" |
| 24 | default XAPIC_ONLY |
| 25 | |
| 26 | config XAPIC_ONLY |
| 27 | prompt "Set XAPIC mode" |
| 28 | bool |
| 29 | |
| 30 | config X2APIC_ONLY |
| 31 | prompt "Set X2APIC mode" |
| 32 | bool |
| 33 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 34 | |
| 35 | config X2APIC_RUNTIME |
| 36 | prompt "Support both XAPIC and X2APIC" |
| 37 | bool |
| 38 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 39 | |
| 40 | endchoice |
| 41 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 42 | config UDELAY_LAPIC |
| 43 | bool |
| 44 | default n |
| 45 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 46 | config LAPIC_MONOTONIC_TIMER |
| 47 | def_bool n |
| 48 | depends on UDELAY_LAPIC |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 49 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 50 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 51 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 52 | config UDELAY_LAPIC_FIXED_FSB |
| 53 | int |
| 54 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 55 | config UDELAY_TSC |
| 56 | bool |
| 57 | default n |
| 58 | |
Kyösti Mälkki | 0d6ddf8 | 2019-10-31 14:52:20 +0200 | [diff] [blame] | 59 | config UNKNOWN_TSC_RATE |
| 60 | bool |
| 61 | default y if LAPIC_MONOTONIC_TIMER |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 62 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 63 | config TSC_MONOTONIC_TIMER |
| 64 | def_bool n |
| 65 | depends on UDELAY_TSC |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 66 | help |
| 67 | Expose monotonic time using the TSC. |
| 68 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 69 | config TSC_SYNC_LFENCE |
| 70 | bool |
| 71 | default n |
| 72 | help |
| 73 | The CPU driver should select this if the CPU needs |
| 74 | to execute an lfence instruction in order to synchronize |
| 75 | rdtsc. This is true for all modern AMD CPUs. |
| 76 | |
| 77 | config TSC_SYNC_MFENCE |
| 78 | bool |
| 79 | default n |
| 80 | help |
| 81 | The CPU driver should select this if the CPU needs |
| 82 | to execute an mfence instruction in order to synchronize |
| 83 | rdtsc. This is true for all modern Intel CPUs. |
| 84 | |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 85 | config SETUP_XIP_CACHE |
| 86 | bool |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 87 | depends on !NO_XIP_EARLY_STAGES |
| 88 | help |
| 89 | Select this option to set up an MTRR to cache XIP stages loaded |
| 90 | from the bootblock. This is useful on platforms lacking a |
| 91 | non-eviction mode and therefore need to be careful to avoid |
| 92 | eviction. |
| 93 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 94 | config LOGICAL_CPUS |
| 95 | bool |
| 96 | default y |
| 97 | |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 98 | config HAVE_SMI_HANDLER |
| 99 | bool |
| 100 | default n |
| 101 | depends on (SMM_ASEG || SMM_TSEG) |
| 102 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 103 | config NO_SMM |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 104 | bool |
| 105 | default n |
| 106 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 107 | config SMM_ASEG |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 108 | bool |
| 109 | default n |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 110 | depends on !NO_SMM |
| 111 | |
| 112 | config SMM_TSEG |
| 113 | bool |
| 114 | default y |
| 115 | depends on !(NO_SMM || SMM_ASEG) |
| 116 | |
| 117 | if SMM_TSEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 118 | |
| 119 | config SMM_MODULE_HEAP_SIZE |
| 120 | hex |
| 121 | default 0x4000 |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 122 | help |
| 123 | This option determines the size of the heap within the SMM handler |
| 124 | modules. |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 125 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 126 | config SMM_MODULE_STACK_SIZE |
| 127 | hex |
Patrick Rudolph | ed8d777 | 2021-06-12 06:21:27 +0200 | [diff] [blame] | 128 | default 0x800 if ARCH_RAMSTAGE_X86_64 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 129 | default 0x400 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 130 | help |
| 131 | This option determines the size of the stack within the SMM handler |
| 132 | modules. |
| 133 | |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 134 | config SMM_STUB_STACK_SIZE |
| 135 | hex |
| 136 | default 0x400 |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 137 | help |
| 138 | This option determines the size of the stack within the SMM handler |
| 139 | modules. |
| 140 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 141 | endif |
| 142 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 143 | config SMM_LAPIC_REMAP_MITIGATION |
| 144 | bool |
| 145 | default y if NORTHBRIDGE_INTEL_I945 |
| 146 | default y if NORTHBRIDGE_INTEL_GM45 |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 147 | default y if NORTHBRIDGE_INTEL_IRONLAKE |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 148 | default n |
| 149 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 150 | config SERIALIZED_SMM_INITIALIZATION |
| 151 | bool |
| 152 | default n |
| 153 | help |
| 154 | On some CPUs, there is a race condition in SMM. |
| 155 | This can occur when both hyperthreads change SMM state |
| 156 | variables in parallel without coordination. |
| 157 | Setting this option serializes the SMM initialization |
| 158 | to avoid an ugly hang in the boot process at the cost |
| 159 | of a slightly longer boot time. |
| 160 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 161 | config X86_AMD_FIXED_MTRRS |
| 162 | bool |
| 163 | default n |
| 164 | help |
| 165 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 166 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 167 | |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 168 | config X86_INIT_NEED_1_SIPI |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 169 | bool |
| 170 | default n |
| 171 | help |
| 172 | This option limits the number of SIPI signals sent during during the |
| 173 | common AP setup. Intel documentation specifies an INIT SIPI SIPI |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 174 | sequence, however this doesn't work on some AMD and Intel platforms. |
| 175 | These newer AMD and Intel platforms don't need the 10ms wait between |
| 176 | INIT and SIPI, so skip that too to save some time. |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 177 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 178 | config SOC_SETS_MSRS |
| 179 | bool |
| 180 | default n |
| 181 | help |
| 182 | The SoC requires different access methods for reading and writing |
| 183 | the MSRs. Use SoC specific routines to handle the MSR access. |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 184 | |
| 185 | config RESERVE_MTRRS_FOR_OS |
| 186 | bool |
| 187 | default n |
| 188 | help |
| 189 | This option allows a platform to reserve 2 MTRRs for the OS usage. |
| 190 | The Intel SDM documents that the the first 6 MTRRs are intended for |
| 191 | the system BIOS and the last 2 are to be reserved for OS usage. |
| 192 | However, modern OSes use PAT to control cacheability instead of |
| 193 | using MTRRs. |
Raul E Rangel | b2346a5 | 2021-09-22 14:56:51 -0600 | [diff] [blame] | 194 | |
| 195 | config CPU_INFO_V2 |
| 196 | bool |
| 197 | depends on PARALLEL_MP |
| 198 | help |
| 199 | Enables the new method of locating struct cpu_info. This new method |
| 200 | uses the %gs segment to locate the cpu_info pointer. The old method |
| 201 | relied on the stack being CONFIG_STACK_SIZE aligned. |