x86: parallel MP initialization
Provide a common entry point for bringing up the APs
in parallel. This work is based off of the Haswell one
which can be moved over to this in the future. The APs
are brought up and have the BSP's MTRRs duplicated in
their own MTRRs. Additionally, Microcode is loaded before
enabling caching. However, the current microcode loading
support assumes Intel's mechanism.
The infrastructure provides a notion of a flight plan
for the BSP and APs. This allows for flexibility in the
order of operations for a given architecture/chip without
providing any specific policy. Therefore, the chipset
caller can provide the order that is required.
TEST=Built and booted on rambi with baytrail specific patches.
Signed-off-by: Aaron Durbin <firstname.lastname@example.org>
Reviewed-by: Alexandru Gagniuc <email@example.com>
Tested-by: build bot (Jenkins)
6 files changed