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review.coreboot.org / coreboot / 41a2c73b064b6ab68e63dd8ce75ef07561d2857d / . / src / cpu / x86 / Kconfig
blob: 1a4318cbcd0f9aa5f82d8e7bdab3369661d0decc [file] [log] [blame]
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -0700[diff] [blame]1# TODO These two options look too similar
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +0300[diff] [blame]2config PARALLEL_CPU_INIT
Sven Schnellea2701c62012-07-29 17:42:52 +0200[diff] [blame]3 bool
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +0300[diff] [blame]4 default n
Sven Schnellea2701c62012-07-29 17:42:52 +0200[diff] [blame]5
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -0700[diff] [blame]6config PARALLEL_MP
Kyösti Mälkki41a2c732021-05-29 21:23:18 +0300[diff] [blame^]7 def_bool y
8 depends on !LEGACY_SMP_INIT
9 depends on SMP
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -0700[diff] [blame]10 help
11 This option uses common MP infrastructure for bringing up APs
12 in parallel. It additionally provides a more flexible mechanism
13 for sequencing the steps of bringing up the APs.
14
Aaron Durbinb21e3622016-12-07 00:32:19 -0600[diff] [blame]15config PARALLEL_MP_AP_WORK
16 def_bool n
17 depends on PARALLEL_MP
18 help
19 Allow APs to do other work after initialization instead of going
20 to sleep.
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -0700[diff] [blame]21
Kyösti Mälkki41a2c732021-05-29 21:23:18 +0300[diff] [blame^]22config LEGACY_SMP_INIT
23 bool
24
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]25config UDELAY_LAPIC
26 bool
27 default n
28
Aaron Durbinfd8291c2013-04-29 17:18:49 -0500[diff] [blame]29config LAPIC_MONOTONIC_TIMER
30 def_bool n
31 depends on UDELAY_LAPIC
Aaron Durbinfd8291c2013-04-29 17:18:49 -0500[diff] [blame]32 help
Elyes HAOUASd6e96862016-08-21 10:12:15 +0200[diff] [blame]33 Expose monotonic time using the local APIC.
Aaron Durbinfd8291c2013-04-29 17:18:49 -0500[diff] [blame]34
Patrick Georgie135ac52012-11-20 11:53:47 +0100[diff] [blame]35config UDELAY_LAPIC_FIXED_FSB
36 int
37
Ronald G. Minnich669c4a92009-08-29 03:00:51 +0000[diff] [blame]38config UDELAY_TSC
39 bool
40 default n
41
Kyösti Mälkki0d6ddf82019-10-31 14:52:20 +0200[diff] [blame]42config UNKNOWN_TSC_RATE
43 bool
44 default y if LAPIC_MONOTONIC_TIMER
Aaron Durbin8e73b5d2013-05-01 15:27:09 -0500[diff] [blame]45
Aaron Durbine8501642013-04-29 22:22:55 -0500[diff] [blame]46config TSC_MONOTONIC_TIMER
47 def_bool n
48 depends on UDELAY_TSC
Aaron Durbine8501642013-04-29 22:22:55 -0500[diff] [blame]49 help
50 Expose monotonic time using the TSC.
51
Stefan Reinauer0db68202012-08-07 14:44:51 -0700[diff] [blame]52config TSC_SYNC_LFENCE
53 bool
54 default n
55 help
56 The CPU driver should select this if the CPU needs
57 to execute an lfence instruction in order to synchronize
58 rdtsc. This is true for all modern AMD CPUs.
59
60config TSC_SYNC_MFENCE
61 bool
62 default n
63 help
64 The CPU driver should select this if the CPU needs
65 to execute an mfence instruction in order to synchronize
66 rdtsc. This is true for all modern Intel CPUs.
67
Arthur Heymans47be2d92019-10-12 17:32:09 +0200[diff] [blame]68config SETUP_XIP_CACHE
69 bool
Arthur Heymans47be2d92019-10-12 17:32:09 +0200[diff] [blame]70 depends on !NO_XIP_EARLY_STAGES
71 help
72 Select this option to set up an MTRR to cache XIP stages loaded
73 from the bootblock. This is useful on platforms lacking a
74 non-eviction mode and therefore need to be careful to avoid
75 eviction.
76
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000[diff] [blame]77config CPU_ADDR_BITS
78 int
79 default 36
80
81config LOGICAL_CPUS
82 bool
83 default y
84
Kyösti Mälkki4d372c72019-07-08 13:48:57 +0300[diff] [blame]85config HAVE_SMI_HANDLER
86 bool
87 default n
88 depends on (SMM_ASEG || SMM_TSEG)
89
Kyösti Mälkki8abf66e2019-07-08 09:56:00 +0300[diff] [blame]90config NO_SMM
Kyösti Mälkki4d372c72019-07-08 13:48:57 +0300[diff] [blame]91 bool
92 default n
93
Kyösti Mälkki8abf66e2019-07-08 09:56:00 +0300[diff] [blame]94config SMM_ASEG
Duncan Laurie8bb77232012-01-09 22:11:25 -0800[diff] [blame]95 bool
96 default n
Kyösti Mälkki8abf66e2019-07-08 09:56:00 +0300[diff] [blame]97 depends on !NO_SMM
98
99config SMM_TSEG
100 bool
101 default y
102 depends on !(NO_SMM || SMM_ASEG)
103
104if SMM_TSEG
Aaron Durbin50a34642013-01-03 17:38:47 -0600[diff] [blame]105
106config SMM_MODULE_HEAP_SIZE
107 hex
108 default 0x4000
Aaron Durbin50a34642013-01-03 17:38:47 -0600[diff] [blame]109 help
110 This option determines the size of the heap within the SMM handler
111 modules.
Aaron Durbin57686f82013-03-20 15:50:59 -0500[diff] [blame]112
Raul E Rangeld3b83932018-06-12 10:43:09 -0600[diff] [blame]113config SMM_MODULE_STACK_SIZE
114 hex
115 default 0x400
Raul E Rangeld3b83932018-06-12 10:43:09 -0600[diff] [blame]116 help
117 This option determines the size of the stack within the SMM handler
118 modules.
119
Marshall Dawson46fc68472018-10-25 13:01:55 -0600[diff] [blame]120config SMM_STUB_STACK_SIZE
121 hex
122 default 0x400
Marshall Dawson46fc68472018-10-25 13:01:55 -0600[diff] [blame]123 help
124 This option determines the size of the stack within the SMM handler
125 modules.
126
Kyösti Mälkki8abf66e2019-07-08 09:56:00 +0300[diff] [blame]127endif
128
Patrick Georgice2564a2015-09-05 20:21:24 +0200[diff] [blame]129config SMM_LAPIC_REMAP_MITIGATION
130 bool
131 default y if NORTHBRIDGE_INTEL_I945
132 default y if NORTHBRIDGE_INTEL_GM45
Angel Pons95de2312020-02-17 13:08:53 +0100[diff] [blame]133 default y if NORTHBRIDGE_INTEL_IRONLAKE
Patrick Georgice2564a2015-09-05 20:21:24 +0200[diff] [blame]134 default n
135
Damien Zammit149c4c52015-11-28 21:27:05 +1100[diff] [blame]136config SERIALIZED_SMM_INITIALIZATION
137 bool
138 default n
139 help
140 On some CPUs, there is a race condition in SMM.
141 This can occur when both hyperthreads change SMM state
142 variables in parallel without coordination.
143 Setting this option serializes the SMM initialization
144 to avoid an ugly hang in the boot process at the cost
145 of a slightly longer boot time.
146
Aaron Durbin57686f82013-03-20 15:50:59 -0500[diff] [blame]147config X86_AMD_FIXED_MTRRS
148 bool
149 default n
150 help
151 This option informs the MTRR code to use the RdMem and WrMem fields
152 in the fixed MTRR MSRs.
Aaron Durbine0785c02013-10-21 12:15:29 -0500[diff] [blame]153
Marshall Dawson98f43a12019-08-05 16:18:56 -0600[diff] [blame]154config X86_AMD_INIT_SIPI
155 bool
156 default n
157 help
158 This option limits the number of SIPI signals sent during during the
159 common AP setup. Intel documentation specifies an INIT SIPI SIPI
160 sequence, however this doesn't work on some AMD platforms.
161
Lee Leahyae738ac2016-07-24 08:03:37 -0700[diff] [blame]162config SOC_SETS_MSRS
163 bool
164 default n
165 help
166 The SoC requires different access methods for reading and writing
167 the MSRs. Use SoC specific routines to handle the MSR access.
Tim Wawrzynczak6fcc46d2021-04-19 13:47:36 -0600[diff] [blame]168
169config RESERVE_MTRRS_FOR_OS
170 bool
171 default n
172 help
173 This option allows a platform to reserve 2 MTRRs for the OS usage.
174 The Intel SDM documents that the the first 6 MTRRs are intended for
175 the system BIOS and the last 2 are to be reserved for OS usage.
176 However, modern OSes use PAT to control cacheability instead of
177 using MTRRs.