Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 1 | config PARALLEL_MP |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 2 | def_bool y |
| 3 | depends on !LEGACY_SMP_INIT |
| 4 | depends on SMP |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 5 | help |
| 6 | This option uses common MP infrastructure for bringing up APs |
| 7 | in parallel. It additionally provides a more flexible mechanism |
| 8 | for sequencing the steps of bringing up the APs. |
| 9 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 10 | config PARALLEL_MP_AP_WORK |
| 11 | def_bool n |
| 12 | depends on PARALLEL_MP |
| 13 | help |
| 14 | Allow APs to do other work after initialization instead of going |
| 15 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 16 | |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 17 | config LEGACY_SMP_INIT |
| 18 | bool |
| 19 | |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 20 | choice LAPIC_ACCESS_MODE |
| 21 | prompt "APIC operation mode" |
| 22 | default XAPIC_ONLY |
| 23 | |
| 24 | config XAPIC_ONLY |
| 25 | prompt "Set XAPIC mode" |
| 26 | bool |
| 27 | |
| 28 | config X2APIC_ONLY |
| 29 | prompt "Set X2APIC mode" |
| 30 | bool |
| 31 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 32 | |
| 33 | config X2APIC_RUNTIME |
| 34 | prompt "Support both XAPIC and X2APIC" |
| 35 | bool |
| 36 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 37 | |
| 38 | endchoice |
| 39 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 40 | config UDELAY_LAPIC |
| 41 | bool |
| 42 | default n |
| 43 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 44 | config LAPIC_MONOTONIC_TIMER |
| 45 | def_bool n |
| 46 | depends on UDELAY_LAPIC |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 47 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 48 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 49 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 50 | config UDELAY_LAPIC_FIXED_FSB |
| 51 | int |
| 52 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 53 | config UDELAY_TSC |
| 54 | bool |
| 55 | default n |
| 56 | |
Kyösti Mälkki | 0d6ddf8 | 2019-10-31 14:52:20 +0200 | [diff] [blame] | 57 | config UNKNOWN_TSC_RATE |
| 58 | bool |
| 59 | default y if LAPIC_MONOTONIC_TIMER |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 60 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 61 | config TSC_MONOTONIC_TIMER |
| 62 | def_bool n |
| 63 | depends on UDELAY_TSC |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 64 | help |
| 65 | Expose monotonic time using the TSC. |
| 66 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 67 | config TSC_SYNC_LFENCE |
| 68 | bool |
| 69 | default n |
| 70 | help |
| 71 | The CPU driver should select this if the CPU needs |
| 72 | to execute an lfence instruction in order to synchronize |
| 73 | rdtsc. This is true for all modern AMD CPUs. |
| 74 | |
| 75 | config TSC_SYNC_MFENCE |
| 76 | bool |
| 77 | default n |
| 78 | help |
| 79 | The CPU driver should select this if the CPU needs |
| 80 | to execute an mfence instruction in order to synchronize |
| 81 | rdtsc. This is true for all modern Intel CPUs. |
| 82 | |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 83 | config SETUP_XIP_CACHE |
| 84 | bool |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 85 | depends on !NO_XIP_EARLY_STAGES |
| 86 | help |
| 87 | Select this option to set up an MTRR to cache XIP stages loaded |
| 88 | from the bootblock. This is useful on platforms lacking a |
| 89 | non-eviction mode and therefore need to be careful to avoid |
| 90 | eviction. |
| 91 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 92 | config CPU_ADDR_BITS |
| 93 | int |
| 94 | default 36 |
| 95 | |
| 96 | config LOGICAL_CPUS |
| 97 | bool |
| 98 | default y |
| 99 | |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 100 | config HAVE_SMI_HANDLER |
| 101 | bool |
| 102 | default n |
| 103 | depends on (SMM_ASEG || SMM_TSEG) |
| 104 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 105 | config NO_SMM |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 106 | bool |
| 107 | default n |
| 108 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 109 | config SMM_ASEG |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 110 | bool |
| 111 | default n |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 112 | depends on !NO_SMM |
| 113 | |
| 114 | config SMM_TSEG |
| 115 | bool |
| 116 | default y |
| 117 | depends on !(NO_SMM || SMM_ASEG) |
| 118 | |
| 119 | if SMM_TSEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 120 | |
| 121 | config SMM_MODULE_HEAP_SIZE |
| 122 | hex |
| 123 | default 0x4000 |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 124 | help |
| 125 | This option determines the size of the heap within the SMM handler |
| 126 | modules. |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 127 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 128 | config SMM_MODULE_STACK_SIZE |
| 129 | hex |
Patrick Rudolph | ed8d777 | 2021-06-12 06:21:27 +0200 | [diff] [blame^] | 130 | default 0x800 if ARCH_RAMSTAGE_X86_64 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 131 | default 0x400 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 132 | help |
| 133 | This option determines the size of the stack within the SMM handler |
| 134 | modules. |
| 135 | |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 136 | config SMM_STUB_STACK_SIZE |
| 137 | hex |
| 138 | default 0x400 |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 139 | help |
| 140 | This option determines the size of the stack within the SMM handler |
| 141 | modules. |
| 142 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 143 | endif |
| 144 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 145 | config SMM_LAPIC_REMAP_MITIGATION |
| 146 | bool |
| 147 | default y if NORTHBRIDGE_INTEL_I945 |
| 148 | default y if NORTHBRIDGE_INTEL_GM45 |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 149 | default y if NORTHBRIDGE_INTEL_IRONLAKE |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 150 | default n |
| 151 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 152 | config SERIALIZED_SMM_INITIALIZATION |
| 153 | bool |
| 154 | default n |
| 155 | help |
| 156 | On some CPUs, there is a race condition in SMM. |
| 157 | This can occur when both hyperthreads change SMM state |
| 158 | variables in parallel without coordination. |
| 159 | Setting this option serializes the SMM initialization |
| 160 | to avoid an ugly hang in the boot process at the cost |
| 161 | of a slightly longer boot time. |
| 162 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 163 | config X86_AMD_FIXED_MTRRS |
| 164 | bool |
| 165 | default n |
| 166 | help |
| 167 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 168 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 169 | |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 170 | config X86_AMD_INIT_SIPI |
| 171 | bool |
| 172 | default n |
| 173 | help |
| 174 | This option limits the number of SIPI signals sent during during the |
| 175 | common AP setup. Intel documentation specifies an INIT SIPI SIPI |
| 176 | sequence, however this doesn't work on some AMD platforms. |
| 177 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 178 | config SOC_SETS_MSRS |
| 179 | bool |
| 180 | default n |
| 181 | help |
| 182 | The SoC requires different access methods for reading and writing |
| 183 | the MSRs. Use SoC specific routines to handle the MSR access. |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 184 | |
| 185 | config RESERVE_MTRRS_FOR_OS |
| 186 | bool |
| 187 | default n |
| 188 | help |
| 189 | This option allows a platform to reserve 2 MTRRs for the OS usage. |
| 190 | The Intel SDM documents that the the first 6 MTRRs are intended for |
| 191 | the system BIOS and the last 2 are to be reserved for OS usage. |
| 192 | However, modern OSes use PAT to control cacheability instead of |
| 193 | using MTRRs. |