src/soc/intel/skylake/Kconfig

config SOC_INTEL_SKYLAKE
	bool
	help
	  Intel Skylake support

if SOC_INTEL_SKYLAKE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_RAMSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_VERSTAGE_X86_32
	select ACPI_NHLT
	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
	select BOOT_DEVICE_SUPPORTS_WRITES
	select CACHE_MRC_SETTINGS
	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
	select C_ENVIRONMENT_BOOTBLOCK
	select COLLECT_TIMESTAMPS
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select GENERIC_GPIO_LIB
	select HAVE_HARD_RESET
	select HAVE_INTEL_FIRMWARE
	select HAVE_MONOTONIC_TIMER
	select HAVE_SMI_HANDLER
	select IOAPIC
	select MMCONF_SUPPORT
	select MMCONF_SUPPORT_DEFAULT
	select NO_FIXED_XIP_ROM_SIZE
	select MRC_SETTINGS_PROTECT
	select PARALLEL_MP
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select PCIEXP_CLK_PM
	select PCIEXP_L1_SUB_STATE
	select REG_SCRIPT
	select RELOCATABLE_MODULES
	select RELOCATABLE_RAMSTAGE
	select RTC
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
	select SOC_INTEL_COMMON_LPSS_I2C
	select SOC_INTEL_COMMON_NHLT
	select SOC_INTEL_COMMON_RESET
	select SMM_TSEG
	select SMP
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	select TSC_CONSTANT_RATE
	select TSC_SYNC_MFENCE
	select UDELAY_TSC

choice
	prompt "FSP Driver"
	default USE_FSP1_1_DRIVER

config USE_FSP2_0_DRIVER
	bool "Build with FSP 2.0"
	select PLATFORM_USES_FSP2_0
	select ADD_VBT_DATA_FILE
	select SOC_INTEL_COMMON_GFX_OPREGION

config USE_FSP1_1_DRIVER
	bool "Build with FSP 1.1"
	select PLATFORM_USES_FSP1_1
	select GOP_SUPPORT
	select DISPLAY_FSP_ENTRY_POINTS

endchoice

config CHROMEOS
	select CHROMEOS_RAMOOPS_DYNAMIC
	select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
	select SEPARATE_VERSTAGE
	select VBOOT_EC_SLOW_UPDATE if EC_GOOGLE_CHROMEEC
	select VBOOT_OPROM_MATTERS
	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
	select VIRTUAL_DEV_SWITCH

config BOOTBLOCK_RESETS
	string
	default "soc/intel/common/reset.c"

config CBFS_SIZE
	hex
	default 0x200000

config CPU_ADDR_BITS
	int
	default 36

config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
	int
	default 120

config DCACHE_RAM_BASE
	hex "Base address of cache-as-RAM"
	default 0xfef00000

config DCACHE_RAM_SIZE
	hex "Length in bytes of cache-as-RAM"
	default 0x40000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x4000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages.

config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0xC000

config EXCLUDE_NATIVE_SD_INTERFACE
	bool
	default n
	help
	  If you set this option to n, will not use native SD controller.

config HEAP_SIZE
	hex
	default 0x80000

config IED_REGION_SIZE
	hex
	default 0x400000

config MMCONF_BASE_ADDRESS
	hex "MMIO Base Address"
	default 0xe0000000

config MONOTONIC_TIMER_MSR
	def_bool y
	select HAVE_MONOTONIC_TIMER
	help
	  Provide a monotonic timer using the 24MHz MSR counter.

config PRE_GRAPHICS_DELAY
	int "Graphics initialization delay in ms"
	default 0
	help
	  On some systems, coreboot boots so fast that connected monitors
	  (mostly TVs) won't be able to wake up fast enough to talk to the
	  VBIOS. On those systems we need to wait for a bit before executing
	  the VBIOS.

config SERIAL_CPU_INIT
	bool
	default n

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.

config SMM_RESERVED_SIZE
	hex
	default 0x200000

config SMM_TSEG_SIZE
	hex
	default 0x800000

config VGA_BIOS_ID
	string
	default "8086,0406"

config UART_DEBUG
	bool "Enable UART debug port."
	default n
	select BOOTBLOCK_CONSOLE
	select CONSOLE_SERIAL
	select DRIVERS_UART
	select DRIVERS_UART_8250MEM_32
	select NO_UART_ON_SUPERIO

config SKYLAKE_SOC_PCH_H
	bool
	default n
	help
	  Choose this option if you have a PCH-H chipset.

config CHIPSET_BOOTBLOCK_INCLUDE
	string
	default "soc/intel/skylake/bootblock/timestamp.inc"

config NHLT_DMIC_2CH
	bool
	default n
	help
	  Include DSP firmware settings for 2 channel DMIC array.

config NHLT_DMIC_4CH
	bool
	default n
	help
	  Include DSP firmware settings for 4 channel DMIC array.

config NHLT_NAU88L25
	bool
	default n
	help
	  Include DSP firmware settings for nau88l25 headset codec.

config NHLT_MAX98357
	bool
	default n
	help
	  Include DSP firmware settings for max98357 amplifier.

config NHLT_SSM4567
	bool
	default n
	help
	  Include DSP firmware settings for ssm4567 smart amplifier.

config SKIP_FSP_CAR
	bool "Skip cache as RAM setup in FSP"
	default y
	help
	  Skip Cache as RAM setup in FSP.

config SPI_FLASH_INCLUDE_ALL_DRIVERS
	bool
	default n

endif